+++ /dev/null
-From sconklin@canonical.com Fri Jan 29 11:32:08 2010
-From: Steve Conklin <sconklin@canonical.com>
-Date: Fri, 29 Jan 2010 12:56:45 -0600
-Subject: drm/i915: Add display hotplug event on Ironlake
-To: stable@kernel.org
-Cc: Steve Conklin <sconklin@canonical.com>, Eric Anholt <eric@anholt.net>, Zhenyu Wang <zhenyuw@linux.intel.com>
-Message-ID: <1264791405-8169-1-git-send-email-sconklin@canonical.com>
-
-
-commit c650156af34bffa3d3a62c9fe26eee595aab3fd1 upstream
-
-Enable display hotplug irqs from Ibex Peak (PCH).
-
-Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Steve Conklin <sconklin@canonical.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-
----
- drivers/gpu/drm/i915/i915_drv.h | 2 ++
- drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++++++++++++++---
- drivers/gpu/drm/i915/i915_reg.h | 1 +
- 3 files changed, 30 insertions(+), 3 deletions(-)
-
---- a/drivers/gpu/drm/i915/i915_drv.h
-+++ b/drivers/gpu/drm/i915/i915_drv.h
-@@ -211,6 +211,8 @@ typedef struct drm_i915_private {
- u32 gt_irq_mask_reg;
- u32 gt_irq_enable_reg;
- u32 de_irq_enable_reg;
-+ u32 pch_irq_mask_reg;
-+ u32 pch_irq_enable_reg;
-
- u32 hotplug_supported_mask;
- struct work_struct hotplug_work;
---- a/drivers/gpu/drm/i915/i915_irq.c
-+++ b/drivers/gpu/drm/i915/i915_irq.c
-@@ -268,7 +268,7 @@ irqreturn_t igdng_irq_handler(struct drm
- {
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
- int ret = IRQ_NONE;
-- u32 de_iir, gt_iir, de_ier;
-+ u32 de_iir, gt_iir, de_ier, pch_iir;
- struct drm_i915_master_private *master_priv;
-
- /* disable master interrupt before clearing iir */
-@@ -278,8 +278,9 @@ irqreturn_t igdng_irq_handler(struct drm
-
- de_iir = I915_READ(DEIIR);
- gt_iir = I915_READ(GTIIR);
-+ pch_iir = I915_READ(SDEIIR);
-
-- if (de_iir == 0 && gt_iir == 0)
-+ if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
- goto done;
-
- ret = IRQ_HANDLED;
-@@ -303,6 +304,14 @@ irqreturn_t igdng_irq_handler(struct drm
- if (de_iir & DE_GSE)
- ironlake_opregion_gse_intr(dev);
-
-+ /* check event from PCH */
-+ if ((de_iir & DE_PCH_EVENT) &&
-+ (pch_iir & SDE_HOTPLUG_MASK)) {
-+ queue_work(dev_priv->wq, &dev_priv->hotplug_work);
-+ }
-+
-+ /* should clear PCH hotplug event before clear CPU irq */
-+ I915_WRITE(SDEIIR, pch_iir);
- I915_WRITE(GTIIR, gt_iir);
- I915_WRITE(DEIIR, de_iir);
-
-@@ -1004,14 +1013,21 @@ static void igdng_irq_preinstall(struct
- I915_WRITE(GTIMR, 0xffffffff);
- I915_WRITE(GTIER, 0x0);
- (void) I915_READ(GTIER);
-+
-+ /* south display irq */
-+ I915_WRITE(SDEIMR, 0xffffffff);
-+ I915_WRITE(SDEIER, 0x0);
-+ (void) I915_READ(SDEIER);
- }
-
- static int igdng_irq_postinstall(struct drm_device *dev)
- {
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
- /* enable kind of interrupts always enabled */
-- u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE /*| DE_PCH_EVENT */;
-+ u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
- u32 render_mask = GT_USER_INTERRUPT;
-+ u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
-+ SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
-
- dev_priv->irq_mask_reg = ~display_mask;
- dev_priv->de_irq_enable_reg = display_mask;
-@@ -1031,6 +1047,14 @@ static int igdng_irq_postinstall(struct
- I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
- (void) I915_READ(GTIER);
-
-+ dev_priv->pch_irq_mask_reg = ~hotplug_mask;
-+ dev_priv->pch_irq_enable_reg = hotplug_mask;
-+
-+ I915_WRITE(SDEIIR, I915_READ(SDEIIR));
-+ I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
-+ I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
-+ (void) I915_READ(SDEIER);
-+
- return 0;
- }
-
---- a/drivers/gpu/drm/i915/i915_reg.h
-+++ b/drivers/gpu/drm/i915/i915_reg.h
-@@ -2121,6 +2121,7 @@
- #define SDE_PORTC_HOTPLUG (1 << 9)
- #define SDE_PORTB_HOTPLUG (1 << 8)
- #define SDE_SDVOB_HOTPLUG (1 << 6)
-+#define SDE_HOTPLUG_MASK (0xf << 8)
-
- #define SDEISR 0xc4000
- #define SDEIMR 0xc4004