]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
LoongArch: Add sign_extend pattern for 32-bit rotate shift
authorXi Ruoyao <xry111@xry111.site>
Sat, 16 Dec 2023 20:26:23 +0000 (04:26 +0800)
committerXi Ruoyao <xry111@xry111.site>
Sat, 23 Dec 2023 12:58:34 +0000 (20:58 +0800)
Remove a redundant sign extension.

gcc/ChangeLog:

* config/loongarch/loongarch.md (rotrsi3_extend): New
define_insn.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/rotrw.c: New test.

gcc/config/loongarch/loongarch.md
gcc/testsuite/gcc.target/loongarch/rotrw.c [new file with mode: 0644]

index b48e8b5352494b42a21a9b1b19bc99b375257684..7021105b2415651290b7a5ca6db725ae5f232cde 100644 (file)
   [(set_attr "type" "shift,shift")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "rotrsi3_extend"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+       (sign_extend:DI
+         (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
+                      (match_operand:SI 2 "arith_operand" "r,I"))))]
+  "TARGET_64BIT"
+  "rotr%i2.w\t%0,%1,%2"
+  [(set_attr "type" "shift,shift")
+   (set_attr "mode" "SI")])
+
 ;; The following templates were added to generate "bstrpick.d + alsl.d"
 ;; instruction pairs.
 ;; It is required that the values of const_immalsl_operand and
diff --git a/gcc/testsuite/gcc.target/loongarch/rotrw.c b/gcc/testsuite/gcc.target/loongarch/rotrw.c
new file mode 100644 (file)
index 0000000..6ed45e8
--- /dev/null
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "rotr\\.w\t\\\$r4,\\\$r4,\\\$r5" } } */
+/* { dg-final { scan-assembler "rotri\\.w\t\\\$r4,\\\$r4,5" } } */
+/* { dg-final { scan-assembler-not "slli\\.w" } } */
+
+unsigned
+rotr (unsigned a, unsigned b)
+{
+  return a >> b | a << 32 - b;
+}
+
+unsigned
+rotri (unsigned a)
+{
+  return a >> 5 | a << 27;
+}