# Check ADX instructions.
- .allow_index_reg
.text
_start:
adcx 400(%ecx), %eax
.* Assembler messages:
-.*:6: Error: `tcmmimfp16ps' is only supported in 64-bit mode
-.*:7: Error: `tcmmrlfp16ps' is only supported in 64-bit mode
+.*:5: Error: `tcmmimfp16ps' is only supported in 64-bit mode
+.*:6: Error: `tcmmrlfp16ps' is only supported in 64-bit mode
# Check Illegal AMX-COMPLEX instructions
- .allow_index_reg
.text
_start:
tcmmimfp16ps %tmm1, %tmm2, %tmm3
- .allow_index_reg
-
.macro test_insn mnemonic
\mnemonic %xmm2, %xmm4, %xmm2
{evex} \mnemonic %xmm2, %xmm4, %xmm2
# Check 32bit AVX-NE-CONVERT instructions
- .allow_index_reg
.text
_start:
vbcstnebf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
# Check VEX.128 scalar instructions with -mavxscalar=256 -msse2avx
- .allow_index_reg
.text
_start:
# Check 32bit AVX-VNNI-INT8 instructions
- .allow_index_reg
.text
_start:
vpdpbssd %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
- .allow_index_reg
-
.macro test_insn mnemonic
\mnemonic %xmm2, %xmm4, %xmm2
{evex} \mnemonic %xmm2, %xmm4, %xmm2
# Check AVX WIG instructions
- .allow_index_reg
.text
_start:
andn (%eax), %eax, %eax
# Check AVX2 WIG instructions
- .allow_index_reg
.text
_start:
vmovntdqa (%ecx),%ymm4
# Check i386 AVX2 instructions
- .allow_index_reg
.text
_start:
# Check i386 256bit integer AVX instructions
- .allow_index_reg
.text
_start:
# Check 32bit AVX512_4FMAPS instructions
- .allow_index_reg
.text
_start:
v4fmaddps (%ecx), %zmm4, %zmm1 # AVX512_4FMAPS
# Check 32bit AVX512_4VNNIW instructions
- .allow_index_reg
.text
_start:
vp4dpwssd (%ecx), %zmm4, %zmm1 # AVX512_4VNNIW
# Check 32bit AVX512_BF16 instructions
- .allow_index_reg
.text
bf16:
vcvtne2ps2bf16 %zmm4, %zmm5, %zmm6 #AVX512_BF16
.*: Assembler messages:
+.*:5: Error: .*
.*:6: Error: .*
.*:7: Error: .*
-.*:8: Error: .*
+.*:10: Error: .*
.*:11: Error: .*
.*:12: Error: .*
-.*:13: Error: .*
# Check illegal AVX512{BF16,VL} instructions
- .allow_index_reg
.text
_start:
vcvtneps2bf16 0x10000000(%rbp, %r14, 8), %xmm3{%k7} #AVX512{BF16,VL} MASK_ENABLING
# Check 32bit AVX512{BF16,VL} instructions
- .allow_index_reg
.text
bf16:
vcvtne2ps2bf16 %ymm4, %ymm5, %ymm6 #AVX512{BF16,VL}
.*: Assembler messages:
-.*:6: Error: unsupported broadcast for `vcvtpd2ph'
-.*:7: Error: unsupported broadcast for `vcvtuqq2ph'
-.*:8: Error: unsupported broadcast for `vcvtdq2ph'
-.*:9: Error: unsupported broadcast for `vcvtudq2ph'
-.*:10: Error: unsupported broadcast for `vcmpph'
-.*:11: Error: Unsupported broadcast: `\{1to64\}'
-.*:12: Error: unsupported broadcast for `vfmadd132ph'
-.*:13: Error: unsupported broadcast for `vfcmaddcph'
-.*:14: Error: unsupported broadcast for `vfcmulcph'
-.*:15: Error: unsupported broadcast for `vcvtdq2ph'
-.*:16: Error: unsupported broadcast for `vfmaddcph'
+.*:5: Error: unsupported broadcast for `vcvtpd2ph'
+.*:6: Error: unsupported broadcast for `vcvtuqq2ph'
+.*:7: Error: unsupported broadcast for `vcvtdq2ph'
+.*:8: Error: unsupported broadcast for `vcvtudq2ph'
+.*:9: Error: unsupported broadcast for `vcmpph'
+.*:10: Error: Unsupported broadcast: `\{1to64\}'
+.*:11: Error: unsupported broadcast for `vfmadd132ph'
+.*:12: Error: unsupported broadcast for `vfcmaddcph'
+.*:13: Error: unsupported broadcast for `vfcmulcph'
+.*:14: Error: unsupported broadcast for `vcvtdq2ph'
+.*:15: Error: unsupported broadcast for `vfmaddcph'
+.*:16: Error: unsupported broadcast for `vfmulcph'
.*:17: Error: unsupported broadcast for `vfmulcph'
-.*:18: Error: unsupported broadcast for `vfmulcph'
-.*:21: Error: unsupported broadcast for `vcvtpd2ph'
-.*:22: Error: unsupported broadcast for `vcvtuqq2ph'
-.*:23: Error: unsupported broadcast for `vcvtdq2ph'
-.*:24: Error: unsupported broadcast for `vcvtudq2ph'
-.*:25: Error: unsupported broadcast for `vcmpph'
-.*:26: Error: Unsupported broadcast: `\{1to64\}'
-.*:27: Error: unsupported broadcast for `vfmsubadd231ph'
-.*:28: Error: unsupported broadcast for `vfcmaddcph'
-.*:29: Error: unsupported broadcast for `vfcmulcph'
-.*:30: Error: unsupported broadcast for `vcvtdq2ph'
-.*:31: Error: unsupported broadcast for `vfcmaddcph'
+.*:20: Error: unsupported broadcast for `vcvtpd2ph'
+.*:21: Error: unsupported broadcast for `vcvtuqq2ph'
+.*:22: Error: unsupported broadcast for `vcvtdq2ph'
+.*:23: Error: unsupported broadcast for `vcvtudq2ph'
+.*:24: Error: unsupported broadcast for `vcmpph'
+.*:25: Error: Unsupported broadcast: `\{1to64\}'
+.*:26: Error: unsupported broadcast for `vfmsubadd231ph'
+.*:27: Error: unsupported broadcast for `vfcmaddcph'
+.*:28: Error: unsupported broadcast for `vfcmulcph'
+.*:29: Error: unsupported broadcast for `vcvtdq2ph'
+.*:30: Error: unsupported broadcast for `vfcmaddcph'
+.*:31: Error: unsupported broadcast for `vfmulcph'
.*:32: Error: unsupported broadcast for `vfmulcph'
-.*:33: Error: unsupported broadcast for `vfmulcph'
# Check error for invalid {1toXX} and {2toXX} broadcasts.
- .allow_index_reg
.text
_start:
vcvtpd2ph (%ecx){1to16}, %xmm3
# Check 32bit AVX512-FP16 instructions
- .allow_index_reg
.text
_start:
vaddph %zmm4, %zmm5, %zmm6 #AVX512-FP16
# Check 32bit VCM.*{PH,SH} instructions
- .allow_index_reg
.text
_start:
vcmpeq_oqph %zmm5, %zmm6, %k5
# Check 32bit AVX512-FP16,AVX512VL instructions
- .allow_index_reg
.text
_start:
vaddph %ymm4, %ymm5, %ymm6 #AVX512-FP16,AVX512VL
# Check 32bit AVX512_VPOPCNTDQ instructions
- .allow_index_reg
.text
vpopcnt:
vpopcntd %zmm5, %zmm6 # AVX512_VPOPCNTDQ
# Check 32bit AVX512BITALG instructions
- .allow_index_reg
.text
bitalg:
vpshufbitqmb %zmm4, %zmm5, %k5 # AVX512BITALG
# Check 32bit AVX512{BITALG,VL} instructions
- .allow_index_reg
.text
bitalg:
vpshufbitqmb %xmm4, %xmm5, %k5{%k7} # AVX512{BITALG,VL}
# Check 32bit AVX512BW swap instructions
- .allow_index_reg
.text
_start:
vmovdqu8 %zmm5, %zmm6 # AVX512BW
# Check 32bit AVX512BW WIG instructions
- .allow_index_reg
.text
_start:
vpabsb %zmm5, %zmm6 # AVX512BW
# Check 32bit AVX512BW instructions
- .allow_index_reg
.text
_start:
vpabsb %zmm5, %zmm6 # AVX512BW
# Check 32bit AVX512{BW,VL} swap instructions
- .allow_index_reg
.text
_start:
vmovdqu8 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
# Check 32bit AVX512{BW,VL} WIG instructions
- .allow_index_reg
.text
_start:
vpabsb %xmm5, %xmm6{%k7} # AVX512{BW,VL}
# Check 32bit AVX512{BW,VL} instructions
- .allow_index_reg
.text
_start:
vpabsb %xmm5, %xmm6{%k7} # AVX512{BW,VL}
# Check 32bit AVX512CD instructions
- .allow_index_reg
.text
cd:
# Check 32bit AVX512{CD,VL} instructions
- .allow_index_reg
.text
cd:
vpconflictd %xmm5, %xmm6{%k7} # AVX512{CD,VL}
# Check 32bit AVX512DQ-RCIG instructions
- .allow_index_reg
.text
_start:
vrangepd $0xab, {sae}, %zmm4, %zmm5, %zmm6 # AVX512DQ
# Check 32bit AVX512DQ instructions
- .allow_index_reg
.text
_start:
vbroadcastf32x8 (%ecx), %zmm6 # AVX512DQ
# Check 32bit AVX512{DQ,VL} instructions
- .allow_index_reg
.text
_start:
vbroadcastf64x2 (%ecx), %ymm6{%k7} # AVX512{DQ,VL}
# Check 32bit AVX512ER-RCIG instructions
- .allow_index_reg
.text
_start:
vexp2ps {sae}, %zmm5, %zmm6 # AVX512ER
# Check 32bit AVX512ER instructions
- .allow_index_reg
.text
_start:
# Check 32bit AVX512F instructions
- .allow_index_reg
.text
_start:
# Check 32bit AVX512F-RCIG instructions
- .allow_index_reg
.text
_start:
vcmppd $0xab, {sae}, %zmm5, %zmm6, %k5 # AVX512F
# Check 32bit AVX512F instructions
- .allow_index_reg
.text
_start:
# Check 32bit AVX512F,GFNI instructions
- .allow_index_reg
.text
_start:
vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
# Check 32bit AVX512F,VAES instructions
- .allow_index_reg
.text
_start:
vaesdec %zmm4, %zmm5, %zmm6 # AVX512F,VAES
# Check 32bit AVX512{F,VL} swap instructions
- .allow_index_reg
.text
_start:
vmovapd %xmm5, %xmm6{%k7} # AVX512{F,VL}
# Check 32bit AVX512{F,VL} WIG instructions
- .allow_index_reg
.text
_start:
vpmovsxbd %xmm5, %xmm6{%k7} # AVX512{F,VL}
# Check 32bit AVX512{F,VL} instructions
- .allow_index_reg
.text
_start:
vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512{F,VL}
# Check 32bit AVX512F,VPCLMULQDQ instructions
- .allow_index_reg
.text
_start:
vpclmulqdq $0xab, %zmm1, %zmm3, %zmm1 # AVX512F,VPCLMULQDQ
# Check 32bit AVX512IFMA instructions
- .allow_index_reg
.text
ifma:
vpmadd52luq %zmm4, %zmm5, %zmm6 # AVX512IFMA
# Check 32bit AVX512{IFMA,VL} instructions
- .allow_index_reg
.text
ifma:
vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
# Check 32bit AVX512PF instructions
- .allow_index_reg
.text
_start:
# Check 32bit AVX512VBMI instructions
- .allow_index_reg
.text
vbmi:
vpermb %zmm4, %zmm5, %zmm6 # AVX512VBMI
# Check 32bit AVX512VBMI2 instructions
- .allow_index_reg
.text
vbmi2:
vpcompressb %zmm6, (%ecx){%k7} # AVX512VBMI2
# Check 32bit AVX512{VBMI2,VL} instructions
- .allow_index_reg
.text
vbmi2:
vpcompressb %xmm6, -123456(%esp,%esi,8){%k7} # AVX512{VBMI2,VL}
# Check 32bit AVX512{VBMI,VL} instructions
- .allow_index_reg
.text
vbmi:
vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
# Check 32bit AVX512VL,GFNI instructions
- .allow_index_reg
.text
_start:
vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
# Check 32bit AVX512VL,VAES instructions
- .allow_index_reg
.text
_start:
vaesdec %xmm4, %xmm5, %xmm6 # AVX512VL,VAES
# Check 32bit AVX512VL,VPCLMULQDQ instructions
- .allow_index_reg
.text
_start:
vpclmulqdq $0xab, %xmm2, %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
# Check 32bit AVX512VNNI instructions
- .allow_index_reg
.text
vnni:
vpdpwssd %zmm3, %zmm1, %zmm4 # AVX512VNNI
# Check 32bit AVX512{VNNI,VL} instructions
- .allow_index_reg
.text
vnni:
vpdpwssd %xmm2, %xmm4, %xmm2{%k3} # AVX512{VNNI,VL}
# Check 32bit BMI instructions
- .allow_index_reg
.text
_start:
# Check 32bit BMI2 instructions
- .allow_index_reg
.text
_start:
# Check 32bit CLDEMOTE instructions
- .allow_index_reg
.text
_start:
# Check 32bit CLFLUSHOPT instructions
- .allow_index_reg
.text
_start:
# Check 32bit CLWB instructions
- .allow_index_reg
.text
_start:
.* Assembler messages:
-.*:6: Error: `cmpbexadd' is only supported in 64-bit mode
-.*:7: Error: `cmpbxadd' is only supported in 64-bit mode
-.*:8: Error: `cmplexadd' is only supported in 64-bit mode
-.*:9: Error: `cmplxadd' is only supported in 64-bit mode
+.*:5: Error: `cmpbexadd' is only supported in 64-bit mode
+.*:6: Error: `cmpbxadd' is only supported in 64-bit mode
+.*:7: Error: `cmplexadd' is only supported in 64-bit mode
+.*:8: Error: `cmplxadd' is only supported in 64-bit mode
# Check Illegal CMPccXADD instructions
- .allow_index_reg
.text
_start:
cmpbexadd %eax, %eax, 0x10000000(%esp, %esi, 8)
.*: Assembler messages:
+.*:5: Error: invalid register operand size for `enqcmd'
.*:6: Error: invalid register operand size for `enqcmd'
-.*:7: Error: invalid register operand size for `enqcmd'
+.*:7: Error: invalid register operand size for `enqcmds'
.*:8: Error: invalid register operand size for `enqcmds'
-.*:9: Error: invalid register operand size for `enqcmds'
+.*:11: Error: invalid register operand size for `enqcmd'
.*:12: Error: invalid register operand size for `enqcmd'
-.*:13: Error: invalid register operand size for `enqcmd'
+.*:13: Error: invalid register operand size for `enqcmds'
.*:14: Error: invalid register operand size for `enqcmds'
-.*:15: Error: invalid register operand size for `enqcmds'
# Check error for ENQCMD[S] 32-bit instructions
- .allow_index_reg
.text
_start:
enqcmd (%si),%eax
# Check ENQCMD[S] 32-bit instructions
- .allow_index_reg
.text
_start:
enqcmd (%ecx),%eax
# Check EVEX non-LIG instructions with with -mevexlig=256
- .allow_index_reg
.text
_start:
{evex} vmovd %xmm4,(%ecx)
# Check EVEX LIG instructions
- .allow_index_reg
.text
_start:
# Check EVEX WIG instructions
- .allow_index_reg
.text
_start:
# Check EVEX instructions
- .allow_index_reg
.text
_start:
.insn EVEX.LIG.F3.0F.W1 0x2a, %eax,{rd-sae},%xmm5,%xmm6
# Check AVX scalar instructions
- .allow_index_reg
.text
_start:
# Check FMA instructions
- .allow_index_reg
.text
_start:
# Check FMA4 instructions
- .allow_index_reg
.text
_start:
# Check GFNI instructions
- .allow_index_reg
.text
_start:
gf2p8mulb %xmm4, %xmm5
# Check 32bit HLE instructions
- .allow_index_reg
.text
_start:
# Check ENQCMD[S] 64-bit instructions in x32 mode
- .allow_index_reg
.text
_start:
enqcmd (%rcx),%rax
# Check MOVDIR[I,64B] 64-bit instructions in x32 mode
- .allow_index_reg
.text
_start:
movdiri %rax, (%rcx)
# Check 64bit LWP instructions
- .allow_index_reg
.text
_start:
# Check MOVDIR[I,64B] 32-bit instructions
- .allow_index_reg
.text
_start:
movdiri %eax, (%ecx)
.*: Assembler messages:
+.*:5: Error: invalid register operand size for `movdir64b'
.*:6: Error: invalid register operand size for `movdir64b'
-.*:7: Error: invalid register operand size for `movdir64b'
+.*:9: Error: invalid register operand size for `movdir64b'
.*:10: Error: invalid register operand size for `movdir64b'
-.*:11: Error: invalid register operand size for `movdir64b'
# Check error for MOVDIR64B 32-bit instructions
- .allow_index_reg
.text
_start:
movdir64b (%si),%eax
.*: Assembler messages:
+.*:5: Error: expecting valid branch instruction after `bnd'
.*:6: Error: expecting valid branch instruction after `bnd'
.*:7: Error: expecting valid branch instruction after `bnd'
+.*:7: Warning: skipping prefixes on `lcall'
.*:8: Error: expecting valid branch instruction after `bnd'
-.*:8: Warning: skipping prefixes on `lcall'
+.*:8: Warning: skipping prefixes on `ljmp'
.*:9: Error: expecting valid branch instruction after `bnd'
-.*:9: Warning: skipping prefixes on `ljmp'
.*:10: Error: expecting valid branch instruction after `bnd'
-.*:11: Error: expecting valid branch instruction after `bnd'
+.*:13: Error: expecting valid branch instruction after `bnd'
.*:14: Error: expecting valid branch instruction after `bnd'
.*:15: Error: expecting valid branch instruction after `bnd'
+.*:15: Warning: skipping prefixes on `lcall'
.*:16: Error: expecting valid branch instruction after `bnd'
-.*:16: Warning: skipping prefixes on `lcall'
+.*:16: Warning: skipping prefixes on `ljmp'
.*:17: Error: expecting valid branch instruction after `bnd'
-.*:17: Warning: skipping prefixes on `ljmp'
.*:18: Error: expecting valid branch instruction after `bnd'
-.*:19: Error: expecting valid branch instruction after `bnd'
GAS LISTING .*
[ ]*1[ ]+\# MPX instructions
-[ ]*2[ ]+\.allow_index_reg
-[ ]*3[ ]+\.text
-[ ]*4[ ]+\.extern xxx
-[ ]*5[ ]+foo:
-[ ]*6[ ]+\?\?\?\? F201C3 bnd add %eax, %ebx \# Bad
+[ ]*2[ ]+\.text
+[ ]*3[ ]+\.extern xxx
+[ ]*4[ ]+foo:
+[ ]*5[ ]+\?\?\?\? F201C3 bnd add %eax, %ebx \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*7[ ]+\?\?\?\? 66F2AB bnd stosw \(%edi\) \# Bad
+[ ]*6[ ]+\?\?\?\? 66F2AB bnd stosw \(%edi\) \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*8[ ]+\?\?\?\? 9A000000 bnd lcall \$0x1234,\$xxx
+[ ]*7[ ]+\?\?\?\? 9A000000 bnd lcall \$0x1234,\$xxx
.* Error: expecting valid branch instruction after `bnd'
.* Warning: skipping prefixes on `lcall'
-[ ]*8[ ]+003412
-[ ]*9[ ]+\?\?\?\? EA000000 bnd ljmp \$0x1234,\$xxx
+[ ]*7[ ]+003412
+[ ]*8[ ]+\?\?\?\? EA000000 bnd ljmp \$0x1234,\$xxx
.* Error: expecting valid branch instruction after `bnd'
.* Warning: skipping prefixes on `ljmp'
-[ ]*9[ ]+003412
-[ ]*10[ ]+\?\?\?\? F2E2E9 bnd loop foo
+[ ]*8[ ]+003412
+[ ]*9[ ]+\?\?\?\? F2E2E9 bnd loop foo
.* Error: expecting valid branch instruction after `bnd'
-[ ]*11[ ]+\?\?\?\? 67F2E3E5 bnd jcxz foo
+[ ]*10[ ]+\?\?\?\? 67F2E3E5 bnd jcxz foo
.* Error: expecting valid branch instruction after `bnd'
-[ ]*12[ ]+
-[ ]*13[ ]+\.intel_syntax noprefix
-[ ]*14[ ]+\?\?\?\? F201C3 bnd add ebx, eax \# Bad
+[ ]*11[ ]+
+[ ]*12[ ]+\.intel_syntax noprefix
+[ ]*13[ ]+\?\?\?\? F201C3 bnd add ebx, eax \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*15[ ]+\?\?\?\? 66F2AB bnd stos WORD PTR\[edi] \# Bad
+[ ]*14[ ]+\?\?\?\? 66F2AB bnd stos WORD PTR\[edi] \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*16[ ]+\?\?\?\? 9A000000 bnd lcall 0x1234,xxx
+[ ]*15[ ]+\?\?\?\? 9A000000 bnd lcall 0x1234,xxx
.* Error: expecting valid branch instruction after `bnd'
.* Warning: skipping prefixes on `lcall'
-[ ]*16[ ]+003412
-[ ]*17[ ]+\?\?\?\? EA000000 bnd ljmp 0x1234,xxx
+[ ]*15[ ]+003412
+[ ]*16[ ]+\?\?\?\? EA000000 bnd ljmp 0x1234,xxx
.* Error: expecting valid branch instruction after `bnd'
.* Warning: skipping prefixes on `ljmp'
-[ ]*17[ ]+003412
-[ ]*18[ ]+\?\?\?\? F2E2CE bnd loop foo
+[ ]*16[ ]+003412
+[ ]*17[ ]+\?\?\?\? F2E2CE bnd loop foo
.* Error: expecting valid branch instruction after `bnd'
-[ ]*19[ ]+\?\?\?\? 67F2E3CA bnd jcxz foo
+[ ]*18[ ]+\?\?\?\? 67F2E3CA bnd jcxz foo
.* Error: expecting valid branch instruction after `bnd'
#pass
# MPX instructions
- .allow_index_reg
.text
.extern xxx
foo:
# MPX instructions
- .allow_index_reg
.text
start:
### bndmk
.* Assembler messages:
-.*:6: Error: `rdmsrlist' is only supported in 64-bit mode
-.*:7: Error: `wrmsrlist' is only supported in 64-bit mode
+.*:5: Error: `rdmsrlist' is only supported in 64-bit mode
+.*:6: Error: `wrmsrlist' is only supported in 64-bit mode
# Check Illegal MSRLIST instructions
- .allow_index_reg
.text
_start:
rdmsrlist #MSRLIST
# Check 32bit NOTRACK prefix
- .allow_index_reg
.text
_start:
notrack call *%eax
.*: Assembler messages:
+.*:5: Error: expecting indirect branch instruction after `notrack'
+.*:5: Warning: skipping prefixes on `call'
.*:6: Error: expecting indirect branch instruction after `notrack'
-.*:6: Warning: skipping prefixes on `call'
-.*:7: Error: expecting indirect branch instruction after `notrack'
+.*:8: Error: same type of prefix used twice
.*:9: Error: same type of prefix used twice
-.*:10: Error: same type of prefix used twice
+.*:12: Error: same type of prefix used twice
.*:13: Error: same type of prefix used twice
-.*:14: Error: same type of prefix used twice
GAS LISTING .*
[ ]*1[ ]+\# Check 32bit unsupported NOTRACK prefix
[ ]*2[ ]+
-[ ]*3[ ]+\.allow_index_reg
-[ ]*4[ ]+\.text
-[ ]*5[ ]+_start:
-[ ]*6[ ]+\?\?\?\? [0-9A-F]* notrack call foo
+[ ]*3[ ]+\.text
+[ ]*4[ ]+_start:
+[ ]*5[ ]+\?\?\?\? [0-9A-F]* notrack call foo
\*\*\*\* Error: expecting indirect branch instruction after `notrack'
\*\*\*\* Warning: skipping prefixes on `call'
-[ ]*6[ ]+[0-9A-F]*
-[ ]*7[ ]+\?\?\?\? [0-9A-F]* notrack jmp foo
+[ ]*5[ ]+[0-9A-F]*
+[ ]*6[ ]+\?\?\?\? [0-9A-F]* notrack jmp foo
\*\*\*\* Error: expecting indirect branch instruction after `notrack'
-[ ]*7[ ]+[0-9A-F]*
-[ ]*8[ ]+
-[ ]*9[ ]+fs notrack call \*%eax
-[ ]*10[ ]+notrack fs call \*%eax
-[ ]*11[ ]+
-[ ]*12[ ]+\.intel_syntax noprefix
-[ ]*13[ ]+fs notrack call eax
-[ ]*14[ ]+notrack fs call eax
+[ ]*6[ ]+[0-9A-F]*
+[ ]*7[ ]+
+[ ]*8[ ]+fs notrack call \*%eax
+[ ]*9[ ]+notrack fs call \*%eax
+[ ]*10[ ]+
+[ ]*11[ ]+\.intel_syntax noprefix
+[ ]*12[ ]+fs notrack call eax
+[ ]*13[ ]+notrack fs call eax
#pass
# Check 32bit unsupported NOTRACK prefix
- .allow_index_reg
.text
_start:
notrack call foo
# Check instructions with optimized encoding
- .allow_index_reg
.text
_start:
vandnpd %zmm1, %zmm1, %zmm5{%k7}
# Check instructions with optimized encoding
- .allow_index_reg
.text
_start:
testl $0x7f, %eax
# Check instructions with optimized encoding
- .allow_index_reg
.text
_start:
{nooptimize} testl $0x7f, %eax
# Check instructions with optimized encoding
- .allow_index_reg
.text
_start:
vandnpd %zmm1, %zmm1, %zmm5{%k7}
.*: Assembler messages:
+.*:5: Error: .*
.*:6: Error: .*
-.*:7: Error: .*
+.*:8: Error: .*
.*:9: Error: .*
-.*:10: Error: .*
+.*:11: Error: .*
.*:12: Error: .*
-.*:13: Error: .*
+.*:14: Error: .*
.*:15: Error: .*
-.*:16: Error: .*
+.*:17: Error: .*
.*:18: Error: .*
-.*:19: Error: .*
+.*:20: Error: .*
.*:21: Error: .*
-.*:22: Error: .*
+.*:23: Error: .*
.*:24: Error: .*
-.*:25: Error: .*
+.*:26: Error: .*
.*:27: Error: .*
-.*:28: Error: .*
+.*:29: Error: .*
.*:30: Error: .*
-.*:31: Error: .*
+.*:32: Error: .*
.*:33: Error: .*
-.*:34: Error: .*
+.*:35: Error: .*
.*:36: Error: .*
-.*:37: Error: .*
+.*:38: Error: .*
.*:39: Error: .*
-.*:40: Error: .*
+.*:41: Error: .*
.*:42: Error: .*
-.*:43: Error: .*
+.*:44: Error: .*
.*:45: Error: .*
-.*:46: Error: .*
GAS LISTING .*
[ ]*3[ ]+\.include "optimize-6\.s"
[ ]*1[ ]+\# Check instructions with optimized encoding
[ ]*2[ ]+
-[ ]*3[ ]+\.allow_index_reg
-[ ]*4[ ]+\.text
-[ ]*5[ ]+_start:
-[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm5
-[ ]*8[ ]+
-[ ]*9[ ]+vandnps %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*10[ ]+vandnps %zmm1, %zmm1, %zmm5
-[ ]*11[ ]+
-[ ]*12[ ]+vpandnd %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*13[ ]+vpandnd %zmm1, %zmm1, %zmm5
-[ ]*14[ ]+
-[ ]*15[ ]+vpandnq %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*16[ ]+vpandnq %zmm1, %zmm1, %zmm5
-[ ]*17[ ]+
-[ ]*18[ ]+vxorpd %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*19[ ]+vxorpd %zmm1, %zmm1, %zmm5
-[ ]*20[ ]+
-[ ]*21[ ]+vxorps %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*22[ ]+vxorps %zmm1, %zmm1, %zmm5
-[ ]*23[ ]+
-[ ]*24[ ]+vpxord %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*25[ ]+vpxord %zmm1, %zmm1, %zmm5
-[ ]*26[ ]+
-[ ]*27[ ]+vpxorq %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*28[ ]+vpxorq %zmm1, %zmm1, %zmm5
-[ ]*29[ ]+
-[ ]*30[ ]+vpsubb %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*31[ ]+vpsubb %zmm1, %zmm1, %zmm5
-[ ]*32[ ]+
-[ ]*33[ ]+vpsubw %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*34[ ]+vpsubw %zmm1, %zmm1, %zmm5
-[ ]*35[ ]+
-[ ]*36[ ]+vpsubd %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*37[ ]+vpsubd %zmm1, %zmm1, %zmm5
-[ ]*38[ ]+
-[ ]*39[ ]+vpsubq %zmm1, %zmm1, %zmm5\{%k7\}
-[ ]*40[ ]+vpsubq %zmm1, %zmm1, %zmm5
-[ ]*41[ ]+
-[ ]*42[ ]+kxord %k1, %k1, %k5
-[ ]*43[ ]+kxorq %k1, %k1, %k5
-[ ]*44[ ]+
-[ ]*45[ ]+kandnd %k1, %k1, %k5
-[ ]*46[ ]+kandnq %k1, %k1, %k5
+[ ]*3[ ]+\.text
+[ ]*4[ ]+_start:
+[ ]*5[ ]+vandnpd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm5
+[ ]*7[ ]+
+[ ]*8[ ]+vandnps %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*9[ ]+vandnps %zmm1, %zmm1, %zmm5
+[ ]*10[ ]+
+[ ]*11[ ]+vpandnd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*12[ ]+vpandnd %zmm1, %zmm1, %zmm5
+[ ]*13[ ]+
+[ ]*14[ ]+vpandnq %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*15[ ]+vpandnq %zmm1, %zmm1, %zmm5
+[ ]*16[ ]+
+[ ]*17[ ]+vxorpd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*18[ ]+vxorpd %zmm1, %zmm1, %zmm5
+[ ]*19[ ]+
+[ ]*20[ ]+vxorps %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*21[ ]+vxorps %zmm1, %zmm1, %zmm5
+[ ]*22[ ]+
+[ ]*23[ ]+vpxord %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*24[ ]+vpxord %zmm1, %zmm1, %zmm5
+[ ]*25[ ]+
+[ ]*26[ ]+vpxorq %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*27[ ]+vpxorq %zmm1, %zmm1, %zmm5
+[ ]*28[ ]+
+[ ]*29[ ]+vpsubb %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*30[ ]+vpsubb %zmm1, %zmm1, %zmm5
+[ ]*31[ ]+
+[ ]*32[ ]+vpsubw %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*33[ ]+vpsubw %zmm1, %zmm1, %zmm5
+[ ]*34[ ]+
+[ ]*35[ ]+vpsubd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*36[ ]+vpsubd %zmm1, %zmm1, %zmm5
+[ ]*37[ ]+
+[ ]*38[ ]+vpsubq %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*39[ ]+vpsubq %zmm1, %zmm1, %zmm5
+[ ]*40[ ]+
+[ ]*41[ ]+kxord %k1, %k1, %k5
+[ ]*42[ ]+kxorq %k1, %k1, %k5
+[ ]*43[ ]+
+[ ]*44[ ]+kandnd %k1, %k1, %k5
+[ ]*45[ ]+kandnq %k1, %k1, %k5
#pass
.*: Assembler messages:
-.*:6: Error: .*
+.*:5: Error: .*
GAS LISTING .*
[ ]*1[ ]+\# Check instructions with optimized encoding
[ ]*2[ ]+
-[ ]*3[ ]+\.allow_index_reg
-[ ]*4[ ]+\.text
-[ ]*5[ ]+_start:
-[ ]*6[ ]+vmovdqa32 %ymm1, %ymm2
+[ ]*3[ ]+\.text
+[ ]*4[ ]+_start:
+[ ]*5[ ]+vmovdqa32 %ymm1, %ymm2
#pass
# Check instructions with optimized encoding
- .allow_index_reg
.text
_start:
vmovdqa32 %ymm1, %ymm2
# Check instructions with encoding options
- .allow_index_reg
.text
_start:
-# Check 32bit AVX512PF instructions
+# Check 32bit PREFETCHWT1 instructions
- .allow_index_reg
.text
_start:
# Check 32bit RAO-INT instructions
- .allow_index_reg
.text
_start:
aadd %edx, (%eax) #RAO-INT
# Check SHA instructions
- .allow_index_reg
.text
_start:
sha1rnds4 $9, %xmm2, %xmm1
# Check SSE to AVX instructions
- .allow_index_reg
.text
_start:
# Tests for op mem64
- .allow_index_reg
.text
_start:
# Check VAES instructions
- .allow_index_reg
.text
_start:
# Tests for op ymm/mem256, ymm, ymm
# Check VEX non-LIG instructions with with -mavxscalar=256
- .allow_index_reg
.text
_start:
vmovd %eax, %xmm0
.*: Assembler messages:
+.*:5: Error: unsupported broadcast for `vp2intersectd'
.*:6: Error: unsupported broadcast for `vp2intersectd'
.*:7: Error: unsupported broadcast for `vp2intersectd'
-.*:8: Error: unsupported broadcast for `vp2intersectd'
+.*:8: Error: unsupported broadcast for `vp2intersectq'
.*:9: Error: unsupported broadcast for `vp2intersectq'
.*:10: Error: unsupported broadcast for `vp2intersectq'
-.*:11: Error: unsupported broadcast for `vp2intersectq'
+.*:13: Error: unsupported broadcast for `vp2intersectd'
.*:14: Error: unsupported broadcast for `vp2intersectd'
.*:15: Error: unsupported broadcast for `vp2intersectd'
-.*:16: Error: unsupported broadcast for `vp2intersectd'
+.*:16: Error: unsupported broadcast for `vp2intersectq'
.*:17: Error: unsupported broadcast for `vp2intersectq'
.*:18: Error: unsupported broadcast for `vp2intersectq'
-.*:19: Error: unsupported broadcast for `vp2intersectq'
# Check error for invalid {1toXX} and {2toXX} broadcasts.
- .allow_index_reg
.text
_start:
vp2intersectd 8(%eax){1to8}, %xmm2, %k3
# Check VPCLMULQDQ instructions
- .allow_index_reg
.text
_start:
vpclmulqdq $0xab, %ymm4, %ymm5, %ymm6
# Check 64 bit ADX instructions.
- .allow_index_reg
.text
_start:
adcx 400(%ecx), %eax
# Check 64bit AMX-COMPLEX instructions
- .allow_index_reg
.text
_start:
tcmmimfp16ps %tmm4, %tmm5, %tmm6 #AMX-COMPLEX
# Check 64bit AMX-FP16 instructions
- .allow_index_reg
.text
_start:
tdpfp16ps %tmm5, %tmm4, %tmm3
- .allow_index_reg
-
.macro test_insn mnemonic
\mnemonic %xmm12, %xmm4, %xmm2
{evex} \mnemonic %xmm12, %xmm4, %xmm2
# Check 64bit AVX-NE-CONVERT instructions
- .allow_index_reg
.text
_start:
vbcstnebf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
# Check VEX.128 scalar instructions with -mavxscalar=256 -msse2avx
- .allow_index_reg
.text
_start:
movd %xmm4,(%rcx)
# Check 64bit instructions with encoding options
- .allow_index_reg
.text
_start:
# Check 64bit AVX-VNNI-INT8 instructions
- .allow_index_reg
.text
_start:
vpdpbssd %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
- .allow_index_reg
-
.macro test_insn mnemonic
\mnemonic %xmm12, %xmm4, %xmm2
{evex} \mnemonic %xmm12, %xmm4, %xmm2
# Check AVX WIG instructions
- .allow_index_reg
.text
_start:
vaddpd %ymm4,%ymm6,%ymm2
# Check AVX2 WIG instructions
- .allow_index_reg
.text
_start:
vmovntdqa (%rcx),%ymm4
# Check x86-64 AVX2 instructions
- .allow_index_reg
.text
_start:
# Check x86-64 256it integer AVX instructions
- .allow_index_reg
.text
_start:
# Check 64bit AVX512_4FMAPS instructions
- .allow_index_reg
.text
_start:
v4fmaddps (%rcx), %zmm8, %zmm1 # AVX512_4FMAPS
# Check 64bit AVX512_4VNNIW instructions
- .allow_index_reg
.text
_start:
vp4dpwssd (%rcx), %zmm8, %zmm1 # AVX512_4VNNIW
# Check 64bit AVX512_BF16 instructions
- .allow_index_reg
.text
_start:
vcvtne2ps2bf16 %zmm28, %zmm29, %zmm30 #AVX512_BF16
.*: Assembler messages:
+.*:5: Error: .*
.*:6: Error: .*
.*:7: Error: .*
-.*:8: Error: .*
+.*:10: Error: .*
.*:11: Error: .*
.*:12: Error: .*
-.*:13: Error: .*
# Check illegal 64bit AVX512{BF16,VL} instructions
- .allow_index_reg
.text
_start:
vcvtneps2bf16 0x10000000(%rbp, %r14, 8), %xmm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
# Check 64bit AVX512{BF16,VL} instructions
- .allow_index_reg
.text
_start:
vcvtne2ps2bf16 %ymm28, %ymm29, %ymm30 #AVX512{BF16,VL}
.*: Assembler messages:
-.*:6: Error: unsupported broadcast for `vcvtpd2ph'
-.*:7: Error: unsupported broadcast for `vcvtuqq2ph'
-.*:8: Error: unsupported broadcast for `vcvtdq2ph'
-.*:9: Error: unsupported broadcast for `vcvtudq2ph'
-.*:10: Error: unsupported broadcast for `vcmpph'
-.*:11: Error: Unsupported broadcast: `\{1to64\}'
-.*:12: Error: unsupported broadcast for `vfmadd132ph'
-.*:13: Error: unsupported broadcast for `vfcmaddcph'
-.*:14: Error: unsupported broadcast for `vfcmulcph'
-.*:15: Error: unsupported broadcast for `vcvtdq2ph'
-.*:16: Error: unsupported broadcast for `vfmaddcph'
+.*:5: Error: unsupported broadcast for `vcvtpd2ph'
+.*:6: Error: unsupported broadcast for `vcvtuqq2ph'
+.*:7: Error: unsupported broadcast for `vcvtdq2ph'
+.*:8: Error: unsupported broadcast for `vcvtudq2ph'
+.*:9: Error: unsupported broadcast for `vcmpph'
+.*:10: Error: Unsupported broadcast: `\{1to64\}'
+.*:11: Error: unsupported broadcast for `vfmadd132ph'
+.*:12: Error: unsupported broadcast for `vfcmaddcph'
+.*:13: Error: unsupported broadcast for `vfcmulcph'
+.*:14: Error: unsupported broadcast for `vcvtdq2ph'
+.*:15: Error: unsupported broadcast for `vfmaddcph'
+.*:16: Error: unsupported broadcast for `vfmulcph'
.*:17: Error: unsupported broadcast for `vfmulcph'
-.*:18: Error: unsupported broadcast for `vfmulcph'
-.*:21: Error: unsupported broadcast for `vcvtpd2ph'
-.*:22: Error: unsupported broadcast for `vcvtuqq2ph'
-.*:23: Error: unsupported broadcast for `vcvtdq2ph'
-.*:24: Error: unsupported broadcast for `vcvtudq2ph'
-.*:25: Error: unsupported broadcast for `vcmpph'
-.*:26: Error: Unsupported broadcast: `\{1to64\}'
-.*:27: Error: unsupported broadcast for `vfmsubadd231ph'
-.*:28: Error: unsupported broadcast for `vfcmaddcph'
-.*:29: Error: unsupported broadcast for `vfcmulcph'
-.*:30: Error: unsupported broadcast for `vcvtdq2ph'
-.*:31: Error: unsupported broadcast for `vfcmaddcph'
+.*:20: Error: unsupported broadcast for `vcvtpd2ph'
+.*:21: Error: unsupported broadcast for `vcvtuqq2ph'
+.*:22: Error: unsupported broadcast for `vcvtdq2ph'
+.*:23: Error: unsupported broadcast for `vcvtudq2ph'
+.*:24: Error: unsupported broadcast for `vcmpph'
+.*:25: Error: Unsupported broadcast: `\{1to64\}'
+.*:26: Error: unsupported broadcast for `vfmsubadd231ph'
+.*:27: Error: unsupported broadcast for `vfcmaddcph'
+.*:28: Error: unsupported broadcast for `vfcmulcph'
+.*:29: Error: unsupported broadcast for `vcvtdq2ph'
+.*:30: Error: unsupported broadcast for `vfcmaddcph'
+.*:31: Error: unsupported broadcast for `vfmulcph'
.*:32: Error: unsupported broadcast for `vfmulcph'
-.*:33: Error: unsupported broadcast for `vfmulcph'
# Check error for invalid {1toXX} and {2toXX} broadcasts.
- .allow_index_reg
.text
_start:
vcvtpd2ph (%ecx){1to16}, %xmm30
.*: Assembler messages:
+.*:5: Error: destination and source registers must be distinct for `vfcmaddcph'
.*:6: Error: destination and source registers must be distinct for `vfcmaddcph'
.*:7: Error: destination and source registers must be distinct for `vfcmaddcph'
-.*:8: Error: destination and source registers must be distinct for `vfcmaddcph'
-.*:9: Error: destination and source registers must be distinct for `vfcmaddcsh'
-.*:10: Error: destination and source registers must be distinct for `vfmaddcph'
-.*:11: Error: destination and source registers must be distinct for `vfmaddcsh'
-.*:12: Error: destination and source registers must be distinct for `vfcmulcph'
-.*:13: Error: destination and source registers must be distinct for `vfcmulcsh'
-.*:14: Error: destination and source registers must be distinct for `vfmulcph'
-.*:15: Error: destination and source registers must be distinct for `vfmulcsh'
+.*:8: Error: destination and source registers must be distinct for `vfcmaddcsh'
+.*:9: Error: destination and source registers must be distinct for `vfmaddcph'
+.*:10: Error: destination and source registers must be distinct for `vfmaddcsh'
+.*:11: Error: destination and source registers must be distinct for `vfcmulcph'
+.*:12: Error: destination and source registers must be distinct for `vfcmulcsh'
+.*:13: Error: destination and source registers must be distinct for `vfmulcph'
+.*:14: Error: destination and source registers must be distinct for `vfmulcsh'
# Check error for destination and source operands have the same register .
- .allow_index_reg
.text
_start:
vfcmaddcph 8128(%rcx), %zmm29, %zmm29
# Check 64bit AVX512-FP16 instructions
- .allow_index_reg
.text
_start:
vaddph %zmm28, %zmm29, %zmm30 #AVX512-FP16
# Check 64bit VCM.*{PH,SH} instructions
- .allow_index_reg
.text
_start:
vcmpeq_oqph %zmm29, %zmm30, %k5
# Check 64bit AVX512-FP16,AVX512VL instructions
- .allow_index_reg
.text
_start:
vaddph %ymm28, %ymm29, %ymm30 #AVX512-FP16,AVX512VL
# Check 64bit AVX512_VPOPCNTDQ instructions
- .allow_index_reg
.text
_start:
vpopcntd %zmm29, %zmm30 # AVX512_VPOPCNTDQ
# Check 64bit AVX512BITALG instructions
- .allow_index_reg
.text
_start:
vpshufbitqmb %zmm28, %zmm29, %k5 # AVX512BITALG
# Check 64bit AVX512{BITALG,VL} instructions
- .allow_index_reg
.text
_start:
vpshufbitqmb %xmm28, %xmm29, %k5 # AVX512{BITALG,VL}
# Check 64bit AVX512BW swap instructions
- .allow_index_reg
.text
_start:
vmovdqu8 %zmm29, %zmm30 # AVX512BW
# Check 64bit AVX512BW WIG instructions
- .allow_index_reg
.text
_start:
vpabsb %zmm29, %zmm30 # AVX512BW
# Check 64bit AVX512BW instructions
- .allow_index_reg
.text
_start:
vpabsb %zmm29, %zmm30 # AVX512BW
# Check 64bit AVX512{BW,VL} swap instructions
- .allow_index_reg
.text
_start:
vmovdqu8 %xmm29, %xmm30 # AVX512{BW,VL}
# Check 64bit AVX512{BW,VL} WIG instructions
- .allow_index_reg
.text
_start:
vpabsb %xmm29, %xmm30 # AVX512{BW,VL}
# Check 64bit AVX512{BW,VL} instructions
- .allow_index_reg
.text
_start:
vpabsb %xmm29, %xmm30 # AVX512{BW,VL}
# Check 64bit AVX512CD instructions
- .allow_index_reg
.text
_start:
# Check 64bit AVX512{CD,VL} instructions
- .allow_index_reg
.text
_start:
vpconflictd %xmm29, %xmm30 # AVX512{CD,VL}
# Check 64bit AVX512DQ-RCIG instructions
- .allow_index_reg
.text
_start:
vrangepd $0xab, {sae}, %zmm28, %zmm29, %zmm30 # AVX512DQ
# Check 64bit AVX512DQ instructions
- .allow_index_reg
.text
_start:
vbroadcastf32x8 (%rcx), %zmm30 # AVX512DQ
# Check 64bit AVX512{DQ,VL} instructions
- .allow_index_reg
.text
_start:
vbroadcastf64x2 (%rcx), %ymm30 # AVX512{DQ,VL}
# Check 64bit AVX512ER-RCIG instructions
- .allow_index_reg
.text
_start:
vexp2ps {sae}, %zmm29, %zmm30 # AVX512ER
# Check 64bit AVX512ER instructions
- .allow_index_reg
.text
_start:
# Check 64bit AVX512F instructions
- .allow_index_reg
.text
_start:
# Check 64bit AVX512F-RCIG instructions
- .allow_index_reg
.text
_start:
vcmpeqpd {sae}, %zmm29, %zmm30, %k5 # AVX512F
# Check 64bit AVX512F instructions
- .allow_index_reg
.text
_start:
# Check 64bit AVX512F,GFNI instructions
- .allow_index_reg
.text
_start:
vgf2p8affineqb $0xab, %zmm28, %zmm29, %zmm30 # AVX512F,GFNI
# Check 64bit AVX512F,VAES instructions
- .allow_index_reg
.text
_start:
vaesdec %zmm28, %zmm29, %zmm30 # AVX512F,VAES
# Check 64bit AVX512{F,VL} swap instructions
- .allow_index_reg
.text
_start:
vmovapd %xmm29, %xmm30 # AVX512{F,VL}
# Check 64bit AVX512{F,VL} WIG instructions
- .allow_index_reg
.text
_start:
vpmovsxbd %xmm29, %xmm30 # AVX512{F,VL}
# Check 64bit AVX512{F,VL} instructions
- .allow_index_reg
.text
_start:
vaddpd %xmm28, %xmm29, %xmm30 # AVX512{F,VL}
# Check 64bit AVX512F,VPCLMULQDQ instructions
- .allow_index_reg
.text
_start:
vpclmulqdq $0xab, %zmm24, %zmm23, %zmm26 # AVX512F,VPCLMULQDQ
# Check 64bit AVX512IFMA instructions
- .allow_index_reg
.text
_start:
vpmadd52luq %zmm28, %zmm29, %zmm30 # AVX512IFMA
# Check 64bit AVX512{IFMA,VL} instructions
- .allow_index_reg
.text
_start:
vpmadd52luq %xmm28, %xmm29, %xmm30 # AVX512{IFMA,VL}
# Check 64bit AVX512PF instructions
- .allow_index_reg
.text
_start:
# Check 64bit AVX512VBMI instructions
- .allow_index_reg
.text
_start:
vpermb %zmm28, %zmm29, %zmm30 # AVX512VBMI
# Check 64bit AVX512VBMI2 instructions
- .allow_index_reg
.text
_start:
vpcompressb %zmm30, (%rcx){%k7} # AVX512VBMI2
# Check 64bit AVX512{VBMI2,VL} instructions
- .allow_index_reg
.text
_start:
vpcompressb %xmm30, (%rcx){%k7} # AVX512{VBMI2,VL}
# Check 64bit AVX512{VBMI,VL} instructions
- .allow_index_reg
.text
_start:
vpermb %xmm28, %xmm29, %xmm30 # AVX512{VBMI,VL}
# Check 64bit AVX512VL,GFNI instructions
- .allow_index_reg
.text
_start:
vgf2p8affineqb $0xab, %xmm28, %xmm29, %xmm30 # AVX512VL,GFNI
# Check 64bit AVX512VL,VAES instructions
- .allow_index_reg
.text
_start:
vaesdec %xmm28, %xmm29, %xmm30 # AVX512VL,VAES
# Check 64bit AVX512VL,VPCLMULQDQ instructions
- .allow_index_reg
.text
_start:
vpclmulqdq $0xab, %xmm18, %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ
# Check 64bit AVX512VNNI instructions
- .allow_index_reg
.text
_start:
vpdpwssd %zmm17, %zmm18, %zmm18 # AVX512VNNI
# Check 64bit AVX512{VNNI,VL} instructions
- .allow_index_reg
.text
_start:
vpdpwssd %xmm20, %xmm22, %xmm26 # AVX512{VNNI,VL}
# Check AVX GFNI instructions
-.allow_index_reg
-.text
+ .text
_start:
vgf2p8mulb %ymm4, %ymm5, %ymm6
vgf2p8mulb -123456(%rax,%r14,8), %ymm5, %ymm6
vgf2p8affineinvqb $123, -123456(%rax,%r14,8), %xmm5, %xmm6
vgf2p8affineinvqb $123, 126(%rdx), %xmm5, %xmm6
-.intel_syntax noprefix
+ .intel_syntax noprefix
vgf2p8mulb ymm6, ymm5, ymm4
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456]
# Check 64bit BMI instructions
- .allow_index_reg
.text
_start:
# Check 64bit BMI2 instructions
- .allow_index_reg
.text
_start:
# Check 64bit CLDEMOTE instructions
- .allow_index_reg
.text
_start:
# Check 64bit CLFLUSHOPT instructions
- .allow_index_reg
.text
_start:
# Check 64bit CLWB instructions
- .allow_index_reg
.text
_start:
# Check 64bit CMPccXADD instructions
- .allow_index_reg
.text
_start:
cmpbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
.* Assembler messages:
+.*5: Error: invalid register operand size for `enqcmd'
.*6: Error: invalid register operand size for `enqcmd'
.*7: Error: invalid register operand size for `enqcmd'
.*8: Error: invalid register operand size for `enqcmd'
-.*9: Error: invalid register operand size for `enqcmd'
+.*9: Error: invalid register operand size for `enqcmds'
.*10: Error: invalid register operand size for `enqcmds'
.*11: Error: invalid register operand size for `enqcmds'
.*12: Error: invalid register operand size for `enqcmds'
-.*13: Error: invalid register operand size for `enqcmds'
+.*15: Error: invalid register operand size for `enqcmd'
.*16: Error: invalid register operand size for `enqcmd'
-.*17: Error: invalid register operand size for `enqcmd'
+.*17: Error: invalid register operand size for `enqcmds'
.*18: Error: invalid register operand size for `enqcmds'
-.*19: Error: invalid register operand size for `enqcmds'
# Check error for ENQCMD[S] 64-bit instructions
- .allow_index_reg
.text
_start:
enqcmd (%esi),%rax
# Check ENQCMD[S] 64-bit instructions
- .allow_index_reg
.text
_start:
enqcmd (%rcx),%rax
# Check EVEX non-LIG instructions with with -mevexlig=256
- .allow_index_reg
.text
_start:
{evex} vmovd %xmm4,(%rcx)
# Check EVEX LIG instructions
- .allow_index_reg
.text
_start:
# Check EVEX WIG instructions
- .allow_index_reg
.text
_start:
# Check non-WIG EVEX instructions with -mevexwig=1
- .allow_index_reg
.text
_start:
vcvtsi2ss %eax, {rd-sae}, %xmm25, %xmm6
# Check 64bit AVX scalar instructions
- .allow_index_reg
.text
_start:
# Check 64bit FMA instructions
- .allow_index_reg
.text
_start:
# Check 64bit FMA4 instructions
- .allow_index_reg
.text
_start:
# Check 64bit FRED instructions
- .allow_index_reg
.text
_start:
erets #FRED
# Check 64bit GFNI instructions
- .allow_index_reg
.text
_start:
gf2p8mulb %xmm4, %xmm5
# Check 64bit HLE instructions
- .allow_index_reg
.text
_start:
# Check 64bit LKGS instructions
- .allow_index_reg
.text
_start:
lkgs %r12 #LKGS
# Check 64bit LWP instructions
- .allow_index_reg
.text
_start:
# Check MOVDIR[I,64B] 64-bit instructions
- .allow_index_reg
.text
_start:
movdiri %rax, (%rcx)
.*: Assembler messages:
+.*:5: Error: invalid register operand size for `movdir64b'
.*:6: Error: invalid register operand size for `movdir64b'
.*:7: Error: invalid register operand size for `movdir64b'
.*:8: Error: invalid register operand size for `movdir64b'
-.*:9: Error: invalid register operand size for `movdir64b'
+.*:11: Error: invalid register operand size for `movdir64b'
.*:12: Error: invalid register operand size for `movdir64b'
-.*:13: Error: invalid register operand size for `movdir64b'
# Check error for MOVDIR64B 32-bit instructions
- .allow_index_reg
.text
_start:
movdir64b (%esi),%rax
.*: Assembler messages:
+.*:3: Error: expecting valid branch instruction after `bnd'
.*:4: Error: expecting valid branch instruction after `bnd'
.*:5: Error: expecting valid branch instruction after `bnd'
.*:6: Error: expecting valid branch instruction after `bnd'
-.*:7: Error: expecting valid branch instruction after `bnd'
+.*:9: Error: expecting valid branch instruction after `bnd'
.*:10: Error: expecting valid branch instruction after `bnd'
.*:11: Error: expecting valid branch instruction after `bnd'
.*:12: Error: expecting valid branch instruction after `bnd'
-.*:13: Error: expecting valid branch instruction after `bnd'
GAS LISTING .*
[ ]*1[ ]+\# MPX instructions
-[ ]*2[ ]+\.allow_index_reg
-[ ]*3[ ]+\.text
-[ ]*4[ ]+\?\?\?\? F24801C3 bnd add %rax, %rbx \# Bad
+[ ]*2[ ]+\.text
+[ ]*3[ ]+\?\?\?\? F24801C3 bnd add %rax, %rbx \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*5[ ]+\?\?\?\? 6766F2AB bnd stosw \(%edi\) \# Bad
+[ ]*4[ ]+\?\?\?\? 6766F2AB bnd stosw \(%edi\) \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*6[ ]+\?\?\?\? F2E2(00|0A) bnd loop foo
+[ ]*5[ ]+\?\?\?\? F2E2(00|0A) bnd loop foo
.* Error: expecting valid branch instruction after `bnd'
-[ ]*7[ ]+\?\?\?\? F2E3(00|0D) bnd jrcxz foo
+[ ]*6[ ]+\?\?\?\? F2E3(00|0D) bnd jrcxz foo
.* Error: expecting valid branch instruction after `bnd'
-[ ]*8[ ]+
-[ ]*9[ ]+\.intel_syntax noprefix
-[ ]*10[ ]+\?\?\?\? F24801C3 bnd add rbx, rax \# Bad
+[ ]*7[ ]+
+[ ]*8[ ]+\.intel_syntax noprefix
+[ ]*9[ ]+\?\?\?\? F24801C3 bnd add rbx, rax \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*11[ ]+\?\?\?\? 6766F2AB bnd stos WORD PTR \[edi] \# Bad
+[ ]*10[ ]+\?\?\?\? 6766F2AB bnd stos WORD PTR \[edi] \# Bad
.* Error: expecting valid branch instruction after `bnd'
-[ ]*12[ ]+\?\?\?\? F2E2(00|18) bnd loop foo
+[ ]*11[ ]+\?\?\?\? F2E2(00|18) bnd loop foo
.* Error: expecting valid branch instruction after `bnd'
-[ ]*13[ ]+\?\?\?\? F2E3(00|1B)( |90) bnd jrcxz foo
+[ ]*12[ ]+\?\?\?\? F2E3(00|1B)( |90) bnd jrcxz foo
.* Error: expecting valid branch instruction after `bnd'
#pass
# MPX instructions
- .allow_index_reg
.text
bnd add %rax, %rbx # Bad
bnd stosw (%edi) # Bad
.*: Assembler messages:
+.*:5: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: .*
+.*:7: Error: `\(%rip\)' cannot be used here
+.*:8: Error: .*
+.*:11: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:12: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:14: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:15: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:16: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:18: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:19: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:20: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:20: Error: .* `bndcl'
.*:21: Error: .* `bndcl'
-.*:22: Error: .* `bndcl'
+.*:24: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:25: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:26: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:26: Error: .* `bndcu'
.*:27: Error: .* `bndcu'
-.*:28: Error: .* `bndcu'
+.*:30: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:31: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:32: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:32: Error: .* `bndcn'
.*:33: Error: .* `bndcn'
-.*:34: Error: .* `bndcn'
+.*:36: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:37: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:39: Warning: register scaling is being ignored here
-.*:40: Error: `base\(%rip\)' cannot be used here
-.*:41: Error: .*
+.*:38: Warning: register scaling is being ignored here
+.*:39: Error: `base\(%rip\)' cannot be used here
+.*:40: Error: .*
+.*:43: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:46: Warning: register scaling is being ignored here
-.*:47: Error: `base\(%rip\)' cannot be used here
-.*:48: Error: .*
+.*:45: Warning: register scaling is being ignored here
+.*:46: Error: `base\(%rip\)' cannot be used here
+.*:47: Error: .*
+.*:50: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:51: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:53: Error: `\[rip\]' cannot be used here
-.*:54: Error: .*
-.*:55: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:52: Error: `\[rip\]' cannot be used here
+.*:53: Error: .*
+.*:54: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:57: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:58: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:59: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:60: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:61: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:62: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:64: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:65: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:66: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:66: Error: .* `bndcl'
.*:67: Error: .* `bndcl'
-.*:68: Error: .* `bndcl'
+.*:70: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:71: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:72: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:72: Error: .* `bndcu'
.*:73: Error: .* `bndcu'
-.*:74: Error: .* `bndcu'
+.*:76: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:77: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:78: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:78: Error: .* `bndcn'
.*:79: Error: .* `bndcn'
-.*:80: Error: .* `bndcn'
+.*:82: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:83: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:84: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:85: Warning: register scaling is being ignored here
-.*:86: Error: `\[rip\+base\]' cannot be used here
-.*:87: Error: .*
-.*:88: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:84: Warning: register scaling is being ignored here
+.*:85: Error: `\[rip\+base\]' cannot be used here
+.*:86: Error: .*
+.*:87: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:90: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:91: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:92: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:93: Warning: register scaling is being ignored here
-.*:94: Error: `\[rip\+base\]' cannot be used here
-.*:95: Error: .*
-.*:96: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:92: Warning: register scaling is being ignored here
+.*:93: Error: `\[rip\+base\]' cannot be used here
+.*:94: Error: .*
+.*:95: Error: `\[rax\+rsp\]' is not a valid base/index expression
GAS LISTING .*
[ ]*1[ ]+\# MPX instructions
-[ ]*2[ ]+\.allow_index_reg
-[ ]*3[ ]+\.text
-[ ]*4[ ]+
+[ ]*2[ ]+\.text
+[ ]*3[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmk
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0103
[ ]*[1-9][0-9]*[ ]+bndcn %ecx, %bnd1
+[ ]*[1-9][0-9]*[ ]+bndcn %cx, %bnd1
\fGAS LISTING .*
-[ ]*[1-9][0-9]*[ ]+bndcn %cx, %bnd1
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\)
[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
+[ ]*[1-9][0-9]*[ ]+08
\fGAS LISTING .*
-[ ]*[1-9][0-9]*[ ]+08
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0203
# MPX instructions
- .allow_index_reg
.text
### bndmk
# MPX instructions
- .allow_index_reg
.text
start:
### bndmk
# Check 64bit NOTRACK prefix
- .allow_index_reg
.text
_start:
notrack call *%rax
.*: Assembler messages:
+.*:5: Error: expecting indirect branch instruction after `notrack'
+.*:5: Warning: skipping prefixes on `call'
.*:6: Error: expecting indirect branch instruction after `notrack'
-.*:6: Warning: skipping prefixes on `call'
-.*:7: Error: expecting indirect branch instruction after `notrack'
+.*:8: Error: same type of prefix used twice
.*:9: Error: same type of prefix used twice
-.*:10: Error: same type of prefix used twice
+.*:12: Error: same type of prefix used twice
.*:13: Error: same type of prefix used twice
-.*:14: Error: same type of prefix used twice
GAS LISTING .*
[ ]*1[ ]+\# Check 64bit unsupported NOTRACK prefix
[ ]*2[ ]+
-[ ]*3[ ]+\.allow_index_reg
-[ ]*4[ ]+\.text
-[ ]*5[ ]+_start:
-[ ]*6[ ]+\?\?\?\? [0-9A-F]* notrack call foo
+[ ]*3[ ]+\.text
+[ ]*4[ ]+_start:
+[ ]*5[ ]+\?\?\?\? [0-9A-F]* notrack call foo
\*\*\*\* Error: expecting indirect branch instruction after `notrack'
\*\*\*\* Warning: skipping prefixes on `call'
-[ ]*6[ ]+[0-9A-F]*
-[ ]*7[ ]+\?\?\?\? [0-9A-F]* notrack jmp foo
+[ ]*5[ ]+[0-9A-F]*
+[ ]*6[ ]+\?\?\?\? [0-9A-F]* notrack jmp foo
\*\*\*\* Error: expecting indirect branch instruction after `notrack'
-[ ]*7[ ]+[0-9A-F]*
-[ ]*8[ ]+
-[ ]*9[ ]+fs notrack call \*%rax
-[ ]*10[ ]+notrack fs call \*%rax
-[ ]*11[ ]+
-[ ]*12[ ]+\.intel_syntax noprefix
-[ ]*13[ ]+fs notrack call rax
-[ ]*14[ ]+notrack fs call rax
+[ ]*6[ ]+[0-9A-F]*
+[ ]*7[ ]+
+[ ]*8[ ]+fs notrack call \*%rax
+[ ]*9[ ]+notrack fs call \*%rax
+[ ]*10[ ]+
+[ ]*11[ ]+\.intel_syntax noprefix
+[ ]*12[ ]+fs notrack call rax
+[ ]*13[ ]+notrack fs call rax
#pass
# Check 64bit unsupported NOTRACK prefix
- .allow_index_reg
.text
_start:
notrack call foo
# Check 64bit instructions with optimized encoding
- .allow_index_reg
.text
_start:
andq $foo, %rax
# Check 64bit instructions with optimized encoding
- .allow_index_reg
.text
_start:
vandnpd %zmm1, %zmm1, %zmm15{%k7}
# Check 64bit instructions with optimized encoding
- .allow_index_reg
.text
_start:
testq $0x7f, %rax
# Check 64bit instructions with optimized encoding
- .allow_index_reg
.text
_start:
{nooptimize} testl $0x7f, %eax
# Check 64bit instructions with optimized encoding
- .allow_index_reg
.text
_start:
vandnpd %zmm1, %zmm1, %zmm15{%k7}
.*: Assembler messages:
+.*:5: Error: .*
.*:6: Error: .*
.*:7: Error: .*
.*:8: Error: .*
-.*:9: Error: .*
+.*:10: Error: .*
.*:11: Error: .*
.*:12: Error: .*
.*:13: Error: .*
-.*:14: Error: .*
+.*:15: Error: .*
.*:16: Error: .*
.*:17: Error: .*
.*:18: Error: .*
-.*:19: Error: .*
+.*:20: Error: .*
.*:21: Error: .*
.*:22: Error: .*
.*:23: Error: .*
-.*:24: Error: .*
+.*:25: Error: .*
.*:26: Error: .*
.*:27: Error: .*
.*:28: Error: .*
-.*:29: Error: .*
+.*:30: Error: .*
.*:31: Error: .*
.*:32: Error: .*
.*:33: Error: .*
-.*:34: Error: .*
+.*:35: Error: .*
.*:36: Error: .*
.*:37: Error: .*
.*:38: Error: .*
-.*:39: Error: .*
+.*:40: Error: .*
.*:41: Error: .*
.*:42: Error: .*
.*:43: Error: .*
-.*:44: Error: .*
+.*:45: Error: .*
.*:46: Error: .*
.*:47: Error: .*
.*:48: Error: .*
-.*:49: Error: .*
+.*:50: Error: .*
.*:51: Error: .*
.*:52: Error: .*
.*:53: Error: .*
-.*:54: Error: .*
+.*:55: Error: .*
.*:56: Error: .*
.*:57: Error: .*
.*:58: Error: .*
-.*:59: Error: .*
+.*:60: Error: .*
.*:61: Error: .*
.*:62: Error: .*
.*:63: Error: .*
-.*:64: Error: .*
GAS LISTING .*
[ ]*3[ ]+\.include "x86-64-optimize-7\.s"
[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
[ ]*2[ ]+
-[ ]*3[ ]+\.allow_index_reg
-[ ]*4[ ]+\.text
-[ ]*5[ ]+_start:
-[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm15
-[ ]*8[ ]+vandnpd %zmm1, %zmm1, %zmm16
-[ ]*9[ ]+vandnpd %zmm17, %zmm17, %zmm1
-[ ]*10[ ]+
-[ ]*11[ ]+vandnps %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*12[ ]+vandnps %zmm1, %zmm1, %zmm15
-[ ]*13[ ]+vandnps %zmm1, %zmm1, %zmm16
-[ ]*14[ ]+vandnps %zmm17, %zmm17, %zmm1
-[ ]*15[ ]+
-[ ]*16[ ]+vpandnd %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*17[ ]+vpandnd %zmm1, %zmm1, %zmm15
-[ ]*18[ ]+vpandnd %zmm1, %zmm1, %zmm16
-[ ]*19[ ]+vpandnd %zmm17, %zmm17, %zmm1
-[ ]*20[ ]+
-[ ]*21[ ]+vpandnq %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*22[ ]+vpandnq %zmm1, %zmm1, %zmm15
-[ ]*23[ ]+vpandnq %zmm1, %zmm1, %zmm16
-[ ]*24[ ]+vpandnq %zmm17, %zmm17, %zmm1
-[ ]*25[ ]+
-[ ]*26[ ]+vxorpd %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*27[ ]+vxorpd %zmm1, %zmm1, %zmm15
-[ ]*28[ ]+vxorpd %zmm1, %zmm1, %zmm16
-[ ]*29[ ]+vxorpd %zmm17, %zmm17, %zmm1
-[ ]*30[ ]+
-[ ]*31[ ]+vxorps %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*32[ ]+vxorps %zmm1, %zmm1, %zmm15
-[ ]*33[ ]+vxorps %zmm1, %zmm1, %zmm16
-[ ]*34[ ]+vxorps %zmm17, %zmm17, %zmm1
-[ ]*35[ ]+
-[ ]*36[ ]+vpxord %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*37[ ]+vpxord %zmm1, %zmm1, %zmm15
-[ ]*38[ ]+vpxord %zmm1, %zmm1, %zmm16
-[ ]*39[ ]+vpxord %zmm17, %zmm17, %zmm1
-[ ]*40[ ]+
-[ ]*41[ ]+vpxorq %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*42[ ]+vpxorq %zmm1, %zmm1, %zmm15
-[ ]*43[ ]+vpxorq %zmm1, %zmm1, %zmm16
-[ ]*44[ ]+vpxorq %zmm17, %zmm17, %zmm1
-[ ]*45[ ]+
-[ ]*46[ ]+vpsubb %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*47[ ]+vpsubb %zmm1, %zmm1, %zmm15
-[ ]*48[ ]+vpsubb %zmm1, %zmm1, %zmm16
-[ ]*49[ ]+vpsubb %zmm17, %zmm17, %zmm1
-[ ]*50[ ]+
-[ ]*51[ ]+vpsubw %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*52[ ]+vpsubw %zmm1, %zmm1, %zmm15
-[ ]*53[ ]+vpsubw %zmm1, %zmm1, %zmm16
-[ ]*54[ ]+vpsubw %zmm17, %zmm17, %zmm1
+[ ]*3[ ]+\.text
+[ ]*4[ ]+_start:
+[ ]*5[ ]+vandnpd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm15
+[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm16
+[ ]*8[ ]+vandnpd %zmm17, %zmm17, %zmm1
+[ ]*9[ ]+
+[ ]*10[ ]+vandnps %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*11[ ]+vandnps %zmm1, %zmm1, %zmm15
+[ ]*12[ ]+vandnps %zmm1, %zmm1, %zmm16
+[ ]*13[ ]+vandnps %zmm17, %zmm17, %zmm1
+[ ]*14[ ]+
+[ ]*15[ ]+vpandnd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*16[ ]+vpandnd %zmm1, %zmm1, %zmm15
+[ ]*17[ ]+vpandnd %zmm1, %zmm1, %zmm16
+[ ]*18[ ]+vpandnd %zmm17, %zmm17, %zmm1
+[ ]*19[ ]+
+[ ]*20[ ]+vpandnq %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*21[ ]+vpandnq %zmm1, %zmm1, %zmm15
+[ ]*22[ ]+vpandnq %zmm1, %zmm1, %zmm16
+[ ]*23[ ]+vpandnq %zmm17, %zmm17, %zmm1
+[ ]*24[ ]+
+[ ]*25[ ]+vxorpd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*26[ ]+vxorpd %zmm1, %zmm1, %zmm15
+[ ]*27[ ]+vxorpd %zmm1, %zmm1, %zmm16
+[ ]*28[ ]+vxorpd %zmm17, %zmm17, %zmm1
+[ ]*29[ ]+
+[ ]*30[ ]+vxorps %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*31[ ]+vxorps %zmm1, %zmm1, %zmm15
+[ ]*32[ ]+vxorps %zmm1, %zmm1, %zmm16
+[ ]*33[ ]+vxorps %zmm17, %zmm17, %zmm1
+[ ]*34[ ]+
+[ ]*35[ ]+vpxord %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*36[ ]+vpxord %zmm1, %zmm1, %zmm15
+[ ]*37[ ]+vpxord %zmm1, %zmm1, %zmm16
+[ ]*38[ ]+vpxord %zmm17, %zmm17, %zmm1
+[ ]*39[ ]+
+[ ]*40[ ]+vpxorq %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*41[ ]+vpxorq %zmm1, %zmm1, %zmm15
+[ ]*42[ ]+vpxorq %zmm1, %zmm1, %zmm16
+[ ]*43[ ]+vpxorq %zmm17, %zmm17, %zmm1
+[ ]*44[ ]+
+[ ]*45[ ]+vpsubb %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*46[ ]+vpsubb %zmm1, %zmm1, %zmm15
+[ ]*47[ ]+vpsubb %zmm1, %zmm1, %zmm16
+[ ]*48[ ]+vpsubb %zmm17, %zmm17, %zmm1
+[ ]*49[ ]+
+[ ]*50[ ]+vpsubw %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*51[ ]+vpsubw %zmm1, %zmm1, %zmm15
+[ ]*52[ ]+vpsubw %zmm1, %zmm1, %zmm16
+[ ]*53[ ]+vpsubw %zmm17, %zmm17, %zmm1
+[ ]*54[ ]+
\fGAS LISTING .*
-[ ]*55[ ]+
-[ ]*56[ ]+vpsubd %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*57[ ]+vpsubd %zmm1, %zmm1, %zmm15
-[ ]*58[ ]+vpsubd %zmm1, %zmm1, %zmm16
-[ ]*59[ ]+vpsubd %zmm17, %zmm17, %zmm1
-[ ]*60[ ]+
-[ ]*61[ ]+vpsubq %zmm1, %zmm1, %zmm15\{%k7\}
-[ ]*62[ ]+vpsubq %zmm1, %zmm1, %zmm15
-[ ]*63[ ]+vpsubq %zmm1, %zmm1, %zmm16
-[ ]*64[ ]+vpsubq %zmm17, %zmm17, %zmm1
+[ ]*55[ ]+vpsubd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*56[ ]+vpsubd %zmm1, %zmm1, %zmm15
+[ ]*57[ ]+vpsubd %zmm1, %zmm1, %zmm16
+[ ]*58[ ]+vpsubd %zmm17, %zmm17, %zmm1
+[ ]*59[ ]+
+[ ]*60[ ]+vpsubq %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*61[ ]+vpsubq %zmm1, %zmm1, %zmm15
+[ ]*62[ ]+vpsubq %zmm1, %zmm1, %zmm16
+[ ]*63[ ]+vpsubq %zmm17, %zmm17, %zmm1
#pass
.*: Assembler messages:
-.*:6: Error: .*
+.*:5: Error: .*
GAS LISTING .*
[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
[ ]*2[ ]+
-[ ]*3[ ]+\.allow_index_reg
-[ ]*4[ ]+\.text
-[ ]*5[ ]+_start:
-[ ]*6[ ]+vmovdqa32 %ymm1, %ymm2
+[ ]*3[ ]+\.text
+[ ]*4[ ]+_start:
+[ ]*5[ ]+vmovdqa32 %ymm1, %ymm2
#pass
# Check 64bit instructions with optimized encoding
- .allow_index_reg
.text
_start:
vmovdqa32 %ymm1, %ymm2
# Check 64bit instructions with encoding options
- .allow_index_reg
.text
_start:
# Check error for ICACHE-PREFETCH 64-bit instruction
- .allow_index_reg
.text
_start:
prefetchit0 0x12345678(%rax)
# Check 64bit PREFETCHI instructions
- .allow_index_reg
.text
_start:
-# Check 64bit AVX512PF instructions
+# Check 64bit PREFETCHWT1 instructions
- .allow_index_reg
.text
_start:
# Check 64bit RAO_INT instructions
- .allow_index_reg
.text
_start:
aadd %rdx, (%rax) #RAO-INT
# Check SHA instructions
- .allow_index_reg
.text
_start:
sha1rnds4 $9, %xmm2, %xmm1
# Check 64bit SSE to AVX instructions
- .allow_index_reg
.text
_start:
# Tests for op mem64
- .allow_index_reg
.text
_start:
# Check 64bit VAES instructions
- .allow_index_reg
.text
_start:
# Tests for op ymm/mem256, ymm, ymm
# Check VEX non-LIG instructions with with -mavxscalar=256
- .allow_index_reg
.text
_start:
vmovd %eax, %xmm0
.*: Assembler messages:
+.*:5: Error: unsupported broadcast for `vp2intersectd'
.*:6: Error: unsupported broadcast for `vp2intersectd'
.*:7: Error: unsupported broadcast for `vp2intersectd'
-.*:8: Error: unsupported broadcast for `vp2intersectd'
+.*:8: Error: unsupported broadcast for `vp2intersectq'
.*:9: Error: unsupported broadcast for `vp2intersectq'
.*:10: Error: unsupported broadcast for `vp2intersectq'
-.*:11: Error: unsupported broadcast for `vp2intersectq'
+.*:13: Error: unsupported broadcast for `vp2intersectd'
.*:14: Error: unsupported broadcast for `vp2intersectd'
.*:15: Error: unsupported broadcast for `vp2intersectd'
-.*:16: Error: unsupported broadcast for `vp2intersectd'
+.*:16: Error: unsupported broadcast for `vp2intersectq'
.*:17: Error: unsupported broadcast for `vp2intersectq'
.*:18: Error: unsupported broadcast for `vp2intersectq'
-.*:19: Error: unsupported broadcast for `vp2intersectq'
# Check error for invalid {1toXX} and {2toXX} broadcasts.
- .allow_index_reg
.text
_start:
vp2intersectd 8(%rax){1to8}, %zmm2, %k3
+# Check 64bit VPCLMULQDQ instructions
-
- .allow_index_reg
.text
_start:
vpclmulqdq $0xab, %ymm8, %ymm9, %ymm10
# Check XOP instructions (maxcombos=16, maxops=3, archbits=64, seed=1)
- .allow_index_reg
.text
_start:
# Check 64bit XSAVEC instructions
- .allow_index_reg
.text
_start:
# Check 64bit XSAVES instructions
- .allow_index_reg
.text
_start:
# Check XOP instructions (maxcombos=16, maxops=3, archbits=32, seed=1)
- .allow_index_reg
.text
_start:
# Check 32bit XSAVEC instructions
- .allow_index_reg
.text
_start:
# Check 32bit XSAVES instructions
- .allow_index_reg
.text
_start:
projects / thirdparty / binutils-gdb.git / commitdiff
