i386: Enable MMX intrinsics without SSE/SSE2/SSSE3

Since MMX intrinsics are marked with SSE/SSE2/SSSE3 for SSE emulation,
enable them without SSE/SSE2/SSSE3 if MMX is enabled.

Restore TARGET_3DNOW check, which was changed to TARGET_3DNOW_A by
revision 271235.

gcc/

	PR target/90497
	* config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX
	intrinsics without SSE/SSE2/SSSE3.
	* config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW
	check.
	(*mmx_uavgv8qi3): Likewise.

gcc/testsuite/

	PR target/90497
	* gcc.target/i386/pr90497-1.c: New test.
	* gcc.target/i386/pr90497-2.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@271328 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 16b67c49da818f8bc42ec3c066fbbca90e90fd87..b199185527ee0004d5bf0bceff8e3d24d9c3ffaa 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/90497
+       * config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX
+       intrinsics without SSE/SSE2/SSSE3.
+       * config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW
+       check.
+       (*mmx_uavgv8qi3): Likewise.
+
 2019-05-17  Richard Biener  <rguenther@suse.de>
 
        * gimple-pretty-print.c (dump_ternary_rhs): Handle dumping

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index df035607fa7da969761079ec0deebf7f2c9d41fb..f2a82a01899643afbfd699f407bb16df8656b661 100644 (file)
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -10937,8 +10937,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
       && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
     isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
   /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when
-     MMX is disabled.  */
-  if (TARGET_MMX_WITH_SSE)
+     MMX is disabled.  NB: Since MMX intrinsics are marked with
+     SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is
+     enabled.  */
+  if (TARGET_MMX || TARGET_MMX_WITH_SSE)
     {
       if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
           == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 29bcf931836185a233b0a6a598f207404e5b6ecf..adad950fa04d6b4d07768026ebe69ae13d3cc88c 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1745,7 +1745,7 @@
                                  (const_int 1) (const_int 1)]))
            (const_int 1))))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
-   && (TARGET_SSE || TARGET_3DNOW_A)"
+   && (TARGET_SSE || TARGET_3DNOW)"
   "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
 
 (define_insn "*mmx_uavgv8qi3"
@@ -1764,7 +1764,7 @@
                                  (const_int 1) (const_int 1)]))
            (const_int 1))))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
-   && (TARGET_SSE || TARGET_3DNOW_A)
+   && (TARGET_SSE || TARGET_3DNOW)
    && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
 {
   /* These two instructions have the same operation, but their encoding

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f63c04d4cba009c40db9cd1df8b2a2a95e2a339f..d60a7f4a5d09a66537cd0f88872ba681c0ae0693 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2019-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/90497
+       * gcc.target/i386/pr90497-1.c: New test.
+       * gcc.target/i386/pr90497-2.c: Likewise.
+
 2019-05-17  Robin Dapp  <rdapp@linux.ibm.com>
 
        * gcc.target/s390/global-array-element-pic.c: Add -march=z900.

diff --git a/gcc/testsuite/gcc.target/i386/pr90497-1.c b/gcc/testsuite/gcc.target/i386/pr90497-1.c
new file mode 100644 (file)
index 0000000..ed6ded7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90497-1.c
@@ -0,0 +1,12 @@
+/* PR target/90497 */
+/* { dg-do compile } */
+/* { dg-options "-mno-sse -mmmx" { target ia32 } } */
+/* { dg-options "-mno-mmx" { target { ! ia32 } } } */
+
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+
+__v8qi
+foo (__v8qi x, __v8qi y)
+{
+  return __builtin_ia32_pcmpeqb (x, y);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr90497-2.c b/gcc/testsuite/gcc.target/i386/pr90497-2.c
new file mode 100644 (file)
index 0000000..99ee575
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90497-2.c
@@ -0,0 +1,11 @@
+/* PR target/90497 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-sse -m3dnow" } */
+
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+
+__v8qi
+foo (__v8qi x, __v8qi y)
+{
+  return __builtin_ia32_pavgusb (x, y);
+}