]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
RDMA/bnxt_re: Report out of sequence hw counters
authorSelvin Xavier <selvin.xavier@broadcom.com>
Mon, 8 Oct 2018 10:28:00 +0000 (03:28 -0700)
committerJason Gunthorpe <jgg@mellanox.com>
Tue, 16 Oct 2018 06:03:50 +0000 (00:03 -0600)
Expose out of sequence errors received from FW.  This counter is a 32 bit
counter and driver has to accumulate the counter. Stores the previous
value for calculating the difference in the next query.

Also, update the HW statistics structure with new fields.

Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
drivers/infiniband/hw/bnxt_re/hw_counters.c
drivers/infiniband/hw/bnxt_re/hw_counters.h
drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
drivers/infiniband/hw/bnxt_re/qplib_sp.c
drivers/infiniband/hw/bnxt_re/qplib_sp.h
drivers/infiniband/hw/bnxt_re/roce_hsi.h

index e63adf2cae1952e102ab2ab48aeb0d5f24a1e9b0..604b71875f5ff70252d76c8266823ff359116aa2 100644 (file)
@@ -108,7 +108,8 @@ static const char * const bnxt_re_stat_name[] = {
        [BNXT_RE_RES_CQ_LOAD_ERR]       = "res_cq_load_err",
        [BNXT_RE_RES_SRQ_LOAD_ERR]      = "res_srq_load_err",
        [BNXT_RE_RES_TX_PCI_ERR]        = "res_tx_pci_err",
-       [BNXT_RE_RES_RX_PCI_ERR]        = "res_rx_pci_err"
+       [BNXT_RE_RES_RX_PCI_ERR]        = "res_rx_pci_err",
+       [BNXT_RE_OUT_OF_SEQ_ERR]        = "oos_drop_count"
 };
 
 int bnxt_re_ib_get_hw_stats(struct ib_device *ibdev,
@@ -226,6 +227,8 @@ int bnxt_re_ib_get_hw_stats(struct ib_device *ibdev,
                                rdev->stats.res_tx_pci_err;
                stats->value[BNXT_RE_RES_RX_PCI_ERR]    =
                                rdev->stats.res_rx_pci_err;
+               stats->value[BNXT_RE_OUT_OF_SEQ_ERR]    =
+                               rdev->stats.res_oos_drop_count;
        }
 
        return ARRAY_SIZE(bnxt_re_stat_name);
index 2c8a409833421090e08fdd2041a088a803ce4592..76399f477e5c8da4be9c02ed6ca6ae21d9a2c086 100644 (file)
@@ -92,6 +92,7 @@ enum bnxt_re_hw_stats {
        BNXT_RE_RES_SRQ_LOAD_ERR,
        BNXT_RE_RES_TX_PCI_ERR,
        BNXT_RE_RES_RX_PCI_ERR,
+       BNXT_RE_OUT_OF_SEQ_ERR,
        BNXT_RE_NUM_COUNTERS
 };
 
index 46416dfe8830eab1d278bb00159fa93f49258f67..9a8687dc0a79d05ad0ca225fe6b972e27154ddef 100644 (file)
@@ -154,6 +154,8 @@ struct bnxt_qplib_qp_node {
        void *qp_handle;        /* ptr to qplib_qp */
 };
 
+#define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
+
 /* RCFW Communication Channels */
 struct bnxt_qplib_rcfw {
        struct pci_dev          *pdev;
@@ -190,6 +192,8 @@ struct bnxt_qplib_rcfw {
        struct bnxt_qplib_crsq  *crsqe_tbl;
        int qp_tbl_size;
        struct bnxt_qplib_qp_node *qp_tbl;
+       u64 oos_prev;
+       u32 init_oos_stats;
 };
 
 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
index c80f2eaaf1a338725e15efd27210d65225e7a09c..14e2b3c13e5c3c789bf2a22b7ae1a48c0f201346 100644 (file)
@@ -840,6 +840,16 @@ int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw,
        stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err);
        stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err);
        stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err);
+       if (!rcfw->init_oos_stats) {
+               rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
+               rcfw->init_oos_stats = 1;
+       } else {
+               stats->res_oos_drop_count +=
+                               (le64_to_cpu(sb->res_oos_drop_count) -
+                                rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK;
+               rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
+       }
+
 bail:
        bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
        return rc;
index 9d3e8b9949458a4503d6ee942f8abe324c90954e..8079d7f5a0085b063d827fd57aeca6ddbb084c56 100644 (file)
@@ -205,6 +205,16 @@ struct bnxt_qplib_roce_stats {
        /* res_tx_pci_err is 64 b */
        u64 res_rx_pci_err;
        /* res_rx_pci_err is 64 b */
+       u64 res_oos_drop_count;
+       /* res_oos_drop_count */
+       u64     active_qp_count_p0;
+       /* port 0 active qps */
+       u64     active_qp_count_p1;
+       /* port 1 active qps */
+       u64     active_qp_count_p2;
+       /* port 2 active qps */
+       u64     active_qp_count_p3;
+       /* port 3 active qps */
 };
 
 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res,
index 3e5a4f760d0eb6332032f824bf3a9367d1bbd07a..8a9ead419ac28d233190e59b7067e06dd71107de 100644 (file)
@@ -2929,6 +2929,11 @@ struct creq_query_roce_stats_resp_sb {
        __le64  res_srq_load_err;
        __le64  res_tx_pci_err;
        __le64  res_rx_pci_err;
+       __le64  res_oos_drop_count;
+       __le64  active_qp_count_p0;
+       __le64  active_qp_count_p1;
+       __le64  active_qp_count_p2;
+       __le64  active_qp_count_p3;
 };
 
 /* QP error notification event (16 bytes) */