* clk-parent:
clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()
* clk-renesas: (24 commits)
clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP
clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1
clk: renesas: r7s9210: Distinguish clocks by clock type
clk: renesas: rzg2l: Remove unneeded nullify checks
clk: renesas: cpg-mssr: Remove obsolete nullify check
clk: renesas: r9a09g057: Add entries for the DMACs
clk: renesas: r9a09g047: Add CANFD clocks and resets
clk: renesas: r9a09g047: Add CRU0 clocks and resets
clk: renesas: rzv2h: Update error message
clk: renesas: rzg2l: Update error message
clk: renesas: r9a09g047: Add ICU clock/reset
clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
clk: renesas: r9a09g047: Add SDHI clocks/resets
clk: renesas: r8a779h0: Add VSPX clock
clk: renesas: r8a779h0: Add FCPVX clock
clk: renesas: r8a08g045: Check the source of the CPU PLL settings
clk: renesas: r9a09g047: Add WDT clocks and resets
clk: renesas: r8a779h0: Add ISP core clocks
clk: renesas: r8a779g0: Add ISP core clocks
clk: renesas: r8a779a0: Add ISP core clocks
...
* clk-mediatek:
clk: mediatek: Add SMI LARBs reset for MT8188
dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx
dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock
* clk-cleanup:
dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
clk: davinci: remove support for da830
dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
clk: mmp: Fix NULL vs IS_ERR() check
clk: Print an error when clk registration fails
clk: Correct the data types of the variables in clk_calc_new_rates
clk: imgtec: use %pe for better readability of errors while printing
clk: stm32f4: fix an uninitialized variable
clk: keystone: syscon-clk: Do not use syscon helper to build regmap