arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller

Add USB and DWC3 node for tertiary port of SC8280 along with
Multiport interrupts and PHYs.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240429162048.2133512-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0403811264d8cfd3c5afec0c14bb86e8a78afd40..9a00863b3d4177c3d0c4e628038b021ac797089c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3423,6 +3423,88 @@
                        interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               usb_2: usb@a4f8800 {
+                       compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
+                       reg = <0 0x0a4f8800 0 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+                                <&gcc GCC_USB30_MP_MASTER_CLK>,
+                                <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+                                <&gcc GCC_USB30_MP_SLEEP_CLK>,
+                                <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+                                <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+                                <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+                                <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+                                <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+                       clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
+                                     "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
+
+                       assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+                                         <&gcc GCC_USB30_MP_MASTER_CLK>;
+                       assigned-clock-rates = <19200000>, <200000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 127 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 126 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 129 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 128 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 131 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 130 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 133 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 132 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+
+                       interrupt-names = "pwr_event_1", "pwr_event_2",
+                                         "pwr_event_3", "pwr_event_4",
+                                         "hs_phy_1",    "hs_phy_2",
+                                         "hs_phy_3",    "hs_phy_4",
+                                         "dp_hs_phy_1", "dm_hs_phy_1",
+                                         "dp_hs_phy_2", "dm_hs_phy_2",
+                                         "dp_hs_phy_3", "dm_hs_phy_3",
+                                         "dp_hs_phy_4", "dm_hs_phy_4",
+                                         "ss_phy_1",    "ss_phy_2";
+
+                       power-domains = <&gcc USB30_MP_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       resets = <&gcc GCC_USB30_MP_BCR>;
+
+                       interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
+                       interconnect-names = "usb-ddr", "apps-usb";
+
+                       wakeup-source;
+
+                       status = "disabled";
+
+                       usb_2_dwc3: usb@a400000 {
+                               compatible = "snps,dwc3";
+                               reg = <0 0x0a400000 0 0xcd00>;
+                               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                               iommus = <&apps_smmu 0x800 0x0>;
+                               phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
+                                      <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
+                                      <&usb_2_hsphy2>,
+                                      <&usb_2_hsphy3>;
+                               phy-names = "usb2-0", "usb3-0",
+                                           "usb2-1", "usb3-1",
+                                           "usb2-2",
+                                           "usb2-3";
+                               dr_mode = "host";
+                       };
+               };
+
                usb_0: usb@a6f8800 {
                        compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
                        reg = <0 0x0a6f8800 0 0x400>;