MIPS/opcodes: Output thread context registers numerically with MFTR/MTTR

We print MFTR and MTTR instructions' thread context register operand in
disassembly using the ABI name the register number would correspond to
should the targeted register be a general-purpose register.

However in most cases it is wrong, because general-purpose registers are
only referred when the 'u' and 'sel' operands are 1 and 0 respectively.
And even in these cases the MFGPR and MTGPR aliases take precedence over
the corresponding generic instruction encodings, so you won't see the
valid case to normally trigger.

Conversely decoding the thread context register operand numerically is
always valid, so switch to using it.  Adjust test coverage accordingly.

diff --git a/gas/testsuite/gas/mips/mips32-mt.d b/gas/testsuite/gas/mips/mips32-mt.d
index b5140216da20fd6dde38a6ada67989eb1a934bdd..80e11f1b229b08a7b2d96b1d5a2efc0859f4e5dc 100644 (file)
--- a/gas/testsuite/gas/mips/mips32-mt.d
+++ b/gas/testsuite/gas/mips/mips32-mt.d
@@ -574,30 +574,30 @@ Disassembly of section .text:
 0+08d0 <[^>]*> 410e6805        mftc0   t5,\$14,5
 0+08d4 <[^>]*> 410e6806        mftc0   t5,\$14,6
 0+08d8 <[^>]*> 410e6807        mftc0   t5,\$14,7
-0+08dc <[^>]*> 410e6810        mftr    t5,t6,0,0,1
-0+08e0 <[^>]*> 410e6811        mftr    t5,t6,0,1,1
-0+08e4 <[^>]*> 410e6812        mftr    t5,t6,0,2,1
-0+08e8 <[^>]*> 410e6813        mftr    t5,t6,0,3,1
-0+08ec <[^>]*> 410e6814        mftr    t5,t6,0,4,1
-0+08f0 <[^>]*> 410e6815        mftr    t5,t6,0,5,1
-0+08f4 <[^>]*> 410e6816        mftr    t5,t6,0,6,1
-0+08f8 <[^>]*> 410e6817        mftr    t5,t6,0,7,1
+0+08dc <[^>]*> 410e6810        mftr    t5,\$14,0,0,1
+0+08e0 <[^>]*> 410e6811        mftr    t5,\$14,0,1,1
+0+08e4 <[^>]*> 410e6812        mftr    t5,\$14,0,2,1
+0+08e8 <[^>]*> 410e6813        mftr    t5,\$14,0,3,1
+0+08ec <[^>]*> 410e6814        mftr    t5,\$14,0,4,1
+0+08f0 <[^>]*> 410e6815        mftr    t5,\$14,0,5,1
+0+08f4 <[^>]*> 410e6816        mftr    t5,\$14,0,6,1
+0+08f8 <[^>]*> 410e6817        mftr    t5,\$14,0,7,1
 0+08fc <[^>]*> 410e6820        mftgpr  t5,t6
 0+0900 <[^>]*> 410e6821        mftacx  t5,\$ac3
 0+0904 <[^>]*> 410e6822        mftc1   t5,\$f14
 0+0908 <[^>]*> 410e6823        cftc1   t5,\$14
 0+090c <[^>]*> 410e6824        mftc2   t5,\$14
 0+0910 <[^>]*> 410e6825        cftc2   t5,\$14
-0+0914 <[^>]*> 410e6826        mftr    t5,t6,1,6,0
-0+0918 <[^>]*> 410e6827        mftr    t5,t6,1,7,0
-0+091c <[^>]*> 410e6830        mftr    t5,t6,1,0,1
-0+0920 <[^>]*> 410e6831        mftr    t5,t6,1,1,1
+0+0914 <[^>]*> 410e6826        mftr    t5,\$14,1,6,0
+0+0918 <[^>]*> 410e6827        mftr    t5,\$14,1,7,0
+0+091c <[^>]*> 410e6830        mftr    t5,\$14,1,0,1
+0+0920 <[^>]*> 410e6831        mftr    t5,\$14,1,1,1
 0+0924 <[^>]*> 410e6832        mfthc1  t5,\$f14
-0+0928 <[^>]*> 410e6833        mftr    t5,t6,1,3,1
+0+0928 <[^>]*> 410e6833        mftr    t5,\$14,1,3,1
 0+092c <[^>]*> 410e6834        mfthc2  t5,\$14
-0+0930 <[^>]*> 410e6835        mftr    t5,t6,1,5,1
-0+0934 <[^>]*> 410e6836        mftr    t5,t6,1,6,1
-0+0938 <[^>]*> 410e6837        mftr    t5,t6,1,7,1
+0+0930 <[^>]*> 410e6835        mftr    t5,\$14,1,5,1
+0+0934 <[^>]*> 410e6836        mftr    t5,\$14,1,6,1
+0+0938 <[^>]*> 410e6837        mftr    t5,\$14,1,7,1
 0+093c <[^>]*> 418d7000        mttc0   t5,c0_epc
 0+0940 <[^>]*> 418d7001        mttc0   t5,\$14,1
 0+0944 <[^>]*> 418d7002        mttc0   t5,\$14,2
@@ -606,29 +606,29 @@ Disassembly of section .text:
 0+0950 <[^>]*> 418d7005        mttc0   t5,\$14,5
 0+0954 <[^>]*> 418d7006        mttc0   t5,\$14,6
 0+0958 <[^>]*> 418d7007        mttc0   t5,\$14,7
-0+095c <[^>]*> 418d7010        mttr    t5,t6,0,0,1
-0+0960 <[^>]*> 418d7011        mttr    t5,t6,0,1,1
-0+0964 <[^>]*> 418d7012        mttr    t5,t6,0,2,1
-0+0968 <[^>]*> 418d7013        mttr    t5,t6,0,3,1
-0+096c <[^>]*> 418d7014        mttr    t5,t6,0,4,1
-0+0970 <[^>]*> 418d7015        mttr    t5,t6,0,5,1
-0+0974 <[^>]*> 418d7016        mttr    t5,t6,0,6,1
-0+0978 <[^>]*> 418d7017        mttr    t5,t6,0,7,1
+0+095c <[^>]*> 418d7010        mttr    t5,\$14,0,0,1
+0+0960 <[^>]*> 418d7011        mttr    t5,\$14,0,1,1
+0+0964 <[^>]*> 418d7012        mttr    t5,\$14,0,2,1
+0+0968 <[^>]*> 418d7013        mttr    t5,\$14,0,3,1
+0+096c <[^>]*> 418d7014        mttr    t5,\$14,0,4,1
+0+0970 <[^>]*> 418d7015        mttr    t5,\$14,0,5,1
+0+0974 <[^>]*> 418d7016        mttr    t5,\$14,0,6,1
+0+0978 <[^>]*> 418d7017        mttr    t5,\$14,0,7,1
 0+097c <[^>]*> 418d7020        mttgpr  t5,t6
 0+0980 <[^>]*> 418d7021        mttacx  t5,\$ac3
 0+0984 <[^>]*> 418d7022        mttc1   t5,\$f14
 0+0988 <[^>]*> 418d7023        cttc1   t5,\$14
 0+098c <[^>]*> 418d7024        mttc2   t5,\$14
 0+0990 <[^>]*> 418d7025        cttc2   t5,\$14
-0+0994 <[^>]*> 418d7026        mttr    t5,t6,1,6,0
-0+0998 <[^>]*> 418d7027        mttr    t5,t6,1,7,0
-0+099c <[^>]*> 418d7030        mttr    t5,t6,1,0,1
-0+09a0 <[^>]*> 418d7031        mttr    t5,t6,1,1,1
+0+0994 <[^>]*> 418d7026        mttr    t5,\$14,1,6,0
+0+0998 <[^>]*> 418d7027        mttr    t5,\$14,1,7,0
+0+099c <[^>]*> 418d7030        mttr    t5,\$14,1,0,1
+0+09a0 <[^>]*> 418d7031        mttr    t5,\$14,1,1,1
 0+09a4 <[^>]*> 418d7032        mtthc1  t5,\$f14
-0+09a8 <[^>]*> 418d7033        mttr    t5,t6,1,3,1
+0+09a8 <[^>]*> 418d7033        mttr    t5,\$14,1,3,1
 0+09ac <[^>]*> 418d7034        mtthc2  t5,\$14
-0+09b0 <[^>]*> 418d7035        mttr    t5,t6,1,5,1
-0+09b4 <[^>]*> 418d7036        mttr    t5,t6,1,6,1
-0+09b8 <[^>]*> 418d7037        mttr    t5,t6,1,7,1
+0+09b0 <[^>]*> 418d7035        mttr    t5,\$14,1,5,1
+0+09b4 <[^>]*> 418d7036        mttr    t5,\$14,1,6,1
+0+09b8 <[^>]*> 418d7037        mttr    t5,\$14,1,7,1
 0+09bc <[^>]*> 00000140        pause
        \.\.\.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 2ee2983fa6ad9a42dbb6689e0f1dcc4d4788ea45..6389301ea8d4246b15c16bed83000db0b6f50c06 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1420,7 +1420,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfthi",              "d,*",          0x41010021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftlo",              "d",            0x41000021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftlo",              "d,*",          0x41000021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
-{"mftr",               "d,t,!,H,$",    0x41000000, 0xffe007c8, WR_1|TRAP,              0,              0,              MT32,   0 },
+{"mftr",               "d,E,!,H,$",    0x41000000, 0xffe007c8, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"mfc0",               "t,G",          0x40000000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I1,             0,      0 },
 {"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I32,            0,      0 },
 {"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
@@ -1577,7 +1577,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtthi",              "t,&",          0x41800821, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttlo",              "t",            0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttlo",              "t,&",          0x41800021, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
-{"mttr",               "t,d,!,H,$",    0x41800000, 0xffe007c8, RD_1|TRAP,              0,              0,              MT32,   0 },
+{"mttr",               "t,G,!,H,$",    0x41800000, 0xffe007c8, RD_1|TRAP,              0,              0,              MT32,   0 },
 {"mul.d",              "D,V,T",        0x46200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"mul.s",              "D,V,T",        0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"mul.ob",             "X,Y,Q",        0x78000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },