+++ /dev/null
-From 09e23823ae9a3e2d5d20f2e1efe0d6e48cef9129 Mon Sep 17 00:00:00 2001
-From: Elad Nachman <enachman@marvell.com>
-Date: Thu, 22 Feb 2024 21:17:14 +0200
-Subject: mmc: sdhci-xenon: add timeout for PHY init complete
-
-From: Elad Nachman <enachman@marvell.com>
-
-commit 09e23823ae9a3e2d5d20f2e1efe0d6e48cef9129 upstream.
-
-AC5X spec says PHY init complete bit must be polled until zero.
-We see cases in which timeout can take longer than the standard
-calculation on AC5X, which is expected following the spec comment above.
-According to the spec, we must wait as long as it takes for that bit to
-toggle on AC5X.
-Cap that with 100 delay loops so we won't get stuck forever.
-
-Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC")
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Elad Nachman <enachman@marvell.com>
-Link: https://lore.kernel.org/r/20240222191714.1216470-3-enachman@marvell.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/mmc/host/sdhci-xenon-phy.c | 29 ++++++++++++++++++++---------
- 1 file changed, 20 insertions(+), 9 deletions(-)
-
---- a/drivers/mmc/host/sdhci-xenon-phy.c
-+++ b/drivers/mmc/host/sdhci-xenon-phy.c
-@@ -112,6 +112,8 @@
- #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
- #define XENON_LOGIC_TIMING_VALUE 0x00AA8977
-
-+#define XENON_MAX_PHY_TIMEOUT_LOOPS 100
-+
- /*
- * List offset of PHY registers and some special register values
- * in eMMC PHY 5.0 or eMMC PHY 5.1
-@@ -262,18 +264,27 @@ static int xenon_emmc_phy_init(struct sd
- /* get the wait time */
- wait /= clock;
- wait++;
-- /* wait for host eMMC PHY init completes */
-- udelay(wait);
-
-- reg = sdhci_readl(host, phy_regs->timing_adj);
-- reg &= XENON_PHY_INITIALIZAION;
-- if (reg) {
-+ /*
-+ * AC5X spec says bit must be polled until zero.
-+ * We see cases in which timeout can take longer
-+ * than the standard calculation on AC5X, which is
-+ * expected following the spec comment above.
-+ * According to the spec, we must wait as long as
-+ * it takes for that bit to toggle on AC5X.
-+ * Cap that with 100 delay loops so we won't get
-+ * stuck here forever:
-+ */
-+
-+ ret = read_poll_timeout(sdhci_readl, reg,
-+ !(reg & XENON_PHY_INITIALIZAION),
-+ wait, XENON_MAX_PHY_TIMEOUT_LOOPS * wait,
-+ false, host, phy_regs->timing_adj);
-+ if (ret)
- dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
-- wait);
-- return -ETIMEDOUT;
-- }
-+ wait * XENON_MAX_PHY_TIMEOUT_LOOPS);
-
-- return 0;
-+ return ret;
- }
-
- #define ARMADA_3700_SOC_PAD_1_8V 0x1
+++ /dev/null
-From 8e9f25a290ae0016353c9ea13314c95fb3207812 Mon Sep 17 00:00:00 2001
-From: Elad Nachman <enachman@marvell.com>
-Date: Thu, 22 Feb 2024 22:09:30 +0200
-Subject: mmc: sdhci-xenon: fix PHY init clock stability
-
-From: Elad Nachman <enachman@marvell.com>
-
-commit 8e9f25a290ae0016353c9ea13314c95fb3207812 upstream.
-
-Each time SD/mmc phy is initialized, at times, in some of
-the attempts, phy fails to completes its initialization
-which results into timeout error. Per the HW spec, it is
-a pre-requisite to ensure a stable SD clock before a phy
-initialization is attempted.
-
-Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC")
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Elad Nachman <enachman@marvell.com>
-Link: https://lore.kernel.org/r/20240222200930.1277665-1-enachman@marvell.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/mmc/host/sdhci-xenon-phy.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/mmc/host/sdhci-xenon-phy.c
-+++ b/drivers/mmc/host/sdhci-xenon-phy.c
-@@ -14,6 +14,7 @@
- #include <linux/slab.h>
- #include <linux/delay.h>
- #include <linux/ktime.h>
-+#include <linux/iopoll.h>
- #include <linux/of_address.h>
-
- #include "sdhci-pltfm.h"
-@@ -221,6 +222,19 @@ static int xenon_alloc_emmc_phy(struct s
- return 0;
- }
-
-+static int xenon_check_stability_internal_clk(struct sdhci_host *host)
-+{
-+ u32 reg;
-+ int err;
-+
-+ err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE,
-+ 1100, 20000, false, host, SDHCI_CLOCK_CONTROL);
-+ if (err)
-+ dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n");
-+
-+ return err;
-+}
-+
- /*
- * eMMC 5.0/5.1 PHY init/re-init.
- * eMMC PHY init should be executed after:
-@@ -237,6 +251,11 @@ static int xenon_emmc_phy_init(struct sd
- struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
- struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
-
-+ int ret = xenon_check_stability_internal_clk(host);
-+
-+ if (ret)
-+ return ret;
-+
- reg = sdhci_readl(host, phy_regs->timing_adj);
- reg |= XENON_PHY_INITIALIZAION;
- sdhci_writel(host, reg, phy_regs->timing_adj);
wifi-nl80211-reject-iftype-change-with-mesh-id-change.patch
btrfs-dev-replace-properly-validate-device-names.patch
mmc-core-fix-emmc-initialization-with-1-bit-bus-connection.patch
-mmc-sdhci-xenon-add-timeout-for-phy-init-complete.patch
-mmc-sdhci-xenon-fix-phy-init-clock-stability.patch
+++ /dev/null
-From 09e23823ae9a3e2d5d20f2e1efe0d6e48cef9129 Mon Sep 17 00:00:00 2001
-From: Elad Nachman <enachman@marvell.com>
-Date: Thu, 22 Feb 2024 21:17:14 +0200
-Subject: mmc: sdhci-xenon: add timeout for PHY init complete
-
-From: Elad Nachman <enachman@marvell.com>
-
-commit 09e23823ae9a3e2d5d20f2e1efe0d6e48cef9129 upstream.
-
-AC5X spec says PHY init complete bit must be polled until zero.
-We see cases in which timeout can take longer than the standard
-calculation on AC5X, which is expected following the spec comment above.
-According to the spec, we must wait as long as it takes for that bit to
-toggle on AC5X.
-Cap that with 100 delay loops so we won't get stuck forever.
-
-Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC")
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Elad Nachman <enachman@marvell.com>
-Link: https://lore.kernel.org/r/20240222191714.1216470-3-enachman@marvell.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/mmc/host/sdhci-xenon-phy.c | 29 ++++++++++++++++++++---------
- 1 file changed, 20 insertions(+), 9 deletions(-)
-
---- a/drivers/mmc/host/sdhci-xenon-phy.c
-+++ b/drivers/mmc/host/sdhci-xenon-phy.c
-@@ -109,6 +109,8 @@
- #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
- #define XENON_LOGIC_TIMING_VALUE 0x00AA8977
-
-+#define XENON_MAX_PHY_TIMEOUT_LOOPS 100
-+
- /*
- * List offset of PHY registers and some special register values
- * in eMMC PHY 5.0 or eMMC PHY 5.1
-@@ -259,18 +261,27 @@ static int xenon_emmc_phy_init(struct sd
- /* get the wait time */
- wait /= clock;
- wait++;
-- /* wait for host eMMC PHY init completes */
-- udelay(wait);
-
-- reg = sdhci_readl(host, phy_regs->timing_adj);
-- reg &= XENON_PHY_INITIALIZAION;
-- if (reg) {
-+ /*
-+ * AC5X spec says bit must be polled until zero.
-+ * We see cases in which timeout can take longer
-+ * than the standard calculation on AC5X, which is
-+ * expected following the spec comment above.
-+ * According to the spec, we must wait as long as
-+ * it takes for that bit to toggle on AC5X.
-+ * Cap that with 100 delay loops so we won't get
-+ * stuck here forever:
-+ */
-+
-+ ret = read_poll_timeout(sdhci_readl, reg,
-+ !(reg & XENON_PHY_INITIALIZAION),
-+ wait, XENON_MAX_PHY_TIMEOUT_LOOPS * wait,
-+ false, host, phy_regs->timing_adj);
-+ if (ret)
- dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
-- wait);
-- return -ETIMEDOUT;
-- }
-+ wait * XENON_MAX_PHY_TIMEOUT_LOOPS);
-
-- return 0;
-+ return ret;
- }
-
- #define ARMADA_3700_SOC_PAD_1_8V 0x1
+++ /dev/null
-From 8e9f25a290ae0016353c9ea13314c95fb3207812 Mon Sep 17 00:00:00 2001
-From: Elad Nachman <enachman@marvell.com>
-Date: Thu, 22 Feb 2024 22:09:30 +0200
-Subject: mmc: sdhci-xenon: fix PHY init clock stability
-
-From: Elad Nachman <enachman@marvell.com>
-
-commit 8e9f25a290ae0016353c9ea13314c95fb3207812 upstream.
-
-Each time SD/mmc phy is initialized, at times, in some of
-the attempts, phy fails to completes its initialization
-which results into timeout error. Per the HW spec, it is
-a pre-requisite to ensure a stable SD clock before a phy
-initialization is attempted.
-
-Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC")
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Elad Nachman <enachman@marvell.com>
-Link: https://lore.kernel.org/r/20240222200930.1277665-1-enachman@marvell.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/mmc/host/sdhci-xenon-phy.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/mmc/host/sdhci-xenon-phy.c
-+++ b/drivers/mmc/host/sdhci-xenon-phy.c
-@@ -11,6 +11,7 @@
- #include <linux/slab.h>
- #include <linux/delay.h>
- #include <linux/ktime.h>
-+#include <linux/iopoll.h>
- #include <linux/of_address.h>
-
- #include "sdhci-pltfm.h"
-@@ -218,6 +219,19 @@ static int xenon_alloc_emmc_phy(struct s
- return 0;
- }
-
-+static int xenon_check_stability_internal_clk(struct sdhci_host *host)
-+{
-+ u32 reg;
-+ int err;
-+
-+ err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE,
-+ 1100, 20000, false, host, SDHCI_CLOCK_CONTROL);
-+ if (err)
-+ dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n");
-+
-+ return err;
-+}
-+
- /*
- * eMMC 5.0/5.1 PHY init/re-init.
- * eMMC PHY init should be executed after:
-@@ -234,6 +248,11 @@ static int xenon_emmc_phy_init(struct sd
- struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
- struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
-
-+ int ret = xenon_check_stability_internal_clk(host);
-+
-+ if (ret)
-+ return ret;
-+
- reg = sdhci_readl(host, phy_regs->timing_adj);
- reg |= XENON_PHY_INITIALIZAION;
- sdhci_writel(host, reg, phy_regs->timing_adj);
dmaengine-fsl-qdma-fix-soc-may-hang-on-16-byte-unaligned-read.patch
dmaengine-fsl-qdma-init-irq-after-reg-initialization.patch
mmc-core-fix-emmc-initialization-with-1-bit-bus-connection.patch
-mmc-sdhci-xenon-add-timeout-for-phy-init-complete.patch
-mmc-sdhci-xenon-fix-phy-init-clock-stability.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
