bfin.md (ssashiftv2hi3, [...]): Fix output template to use half reg for operand 2.

	* config/bfin/bfin.md (ssashiftv2hi3, ssashifthi3, lshiftv2hi3,
	lshifthi3): Fix output template to use half reg for operand 2.

From-SVN: r122374

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f6b8edb5efac1ffcc28b82be0821fe11b0a25c2f..91852b9f225fe40a26fa22a2f7f063dbf493e8e7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -40,6 +40,9 @@
        usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
        usmulhisi_hh_huh): New patterns.
 
+       * config/bfin/bfin.md (ssashiftv2hi3, ssashifthi3, lshiftv2hi3,
+       lshifthi3): Fix output template to use half reg for operand 2.
+
 2007-02-27  Andreas Schwab  <schwab@suse.de>
 
        * Makefile.in (TEXI_GCCINSTALL_FILES): Add gcc-common.texi.

diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 7bdde27fafb503588f1957f6b3724014fb46c7c0..6786902fac5d5d53f1d7bf1716d90e4452f3dd6d 100644 (file)
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -3777,7 +3777,7 @@
         (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
   ""
   "@
-   %0 = ASHIFT %1 BY %2 (V, S)%!
+   %0 = ASHIFT %1 BY %h2 (V, S)%!
    %0 = %1 << %2 (V,S)%!
    %0 = %1 >>> %N2 (V,S)%!"
   [(set_attr "type" "dsp32")])
@@ -3791,7 +3791,7 @@
         (ss_ashift:HI (match_dup 1) (match_dup 2))))]
   ""
   "@
-   %0 = ASHIFT %1 BY %2 (V, S)%!
+   %0 = ASHIFT %1 BY %h2 (V, S)%!
    %0 = %1 << %2 (V,S)%!
    %0 = %1 >>> %N2 (V,S)%!"
   [(set_attr "type" "dsp32")])
@@ -3805,7 +3805,7 @@
         (ashift:V2HI (match_dup 1) (match_dup 2))))]
   ""
   "@
-   %0 = LSHIFT %1 BY %2 (V)%!
+   %0 = LSHIFT %1 BY %h2 (V)%!
    %0 = %1 << %2 (V)%!
    %0 = %1 >> %N2 (V)%!"
   [(set_attr "type" "dsp32")])
@@ -3819,7 +3819,7 @@
         (ashift:HI (match_dup 1) (match_dup 2))))]
   ""
   "@
-   %0 = LSHIFT %1 BY %2 (V)%!
+   %0 = LSHIFT %1 BY %h2 (V)%!
    %0 = %1 << %2 (V)%!
    %0 = %1 >> %N2 (V)%!"
   [(set_attr "type" "dsp32")])