--- /dev/null
+From c140244f0cfb9601dbc35e7ab90914954a76b3d1 Mon Sep 17 00:00:00 2001
+From: Maciej Falkowski <maciej.falkowski@linux.intel.com>
+Date: Fri, 4 Oct 2024 18:25:04 +0200
+Subject: accel/ivpu: Add initial Panther Lake support
+
+From: Maciej Falkowski <maciej.falkowski@linux.intel.com>
+
+commit c140244f0cfb9601dbc35e7ab90914954a76b3d1 upstream.
+
+Add support for the 5th generation of Intel NPU that
+is going to be present in PTL_P (Panther Lake) CPUs.
+NPU5 code reuses almost all of previous driver code.
+
+Signed-off-by: Maciej Falkowski <maciej.falkowski@linux.intel.com>
+Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20241004162505.1695605-2-maciej.falkowski@linux.intel.com
+Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/accel/ivpu/ivpu_drv.c | 1 +
+ drivers/accel/ivpu/ivpu_drv.h | 10 +++++++---
+ drivers/accel/ivpu/ivpu_fw.c | 3 +++
+ 3 files changed, 11 insertions(+), 3 deletions(-)
+
+--- a/drivers/accel/ivpu/ivpu_drv.c
++++ b/drivers/accel/ivpu/ivpu_drv.c
+@@ -709,6 +709,7 @@ static struct pci_device_id ivpu_pci_ids
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
++ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
+ { }
+ };
+ MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
+--- a/drivers/accel/ivpu/ivpu_drv.h
++++ b/drivers/accel/ivpu/ivpu_drv.h
+@@ -23,9 +23,10 @@
+ #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
+ #define DRIVER_DATE "20230117"
+
+-#define PCI_DEVICE_ID_MTL 0x7d1d
+-#define PCI_DEVICE_ID_ARL 0xad1d
+-#define PCI_DEVICE_ID_LNL 0x643e
++#define PCI_DEVICE_ID_MTL 0x7d1d
++#define PCI_DEVICE_ID_ARL 0xad1d
++#define PCI_DEVICE_ID_LNL 0x643e
++#define PCI_DEVICE_ID_PTL_P 0xb03e
+
+ #define IVPU_HW_IP_37XX 37
+ #define IVPU_HW_IP_40XX 40
+@@ -227,6 +228,8 @@ static inline int ivpu_hw_ip_gen(struct
+ return IVPU_HW_IP_37XX;
+ case PCI_DEVICE_ID_LNL:
+ return IVPU_HW_IP_40XX;
++ case PCI_DEVICE_ID_PTL_P:
++ return IVPU_HW_IP_50XX;
+ default:
+ dump_stack();
+ ivpu_err(vdev, "Unknown NPU IP generation\n");
+@@ -241,6 +244,7 @@ static inline int ivpu_hw_btrs_gen(struc
+ case PCI_DEVICE_ID_ARL:
+ return IVPU_HW_BTRS_MTL;
+ case PCI_DEVICE_ID_LNL:
++ case PCI_DEVICE_ID_PTL_P:
+ return IVPU_HW_BTRS_LNL;
+ default:
+ dump_stack();
+--- a/drivers/accel/ivpu/ivpu_fw.c
++++ b/drivers/accel/ivpu/ivpu_fw.c
+@@ -57,11 +57,14 @@ static struct {
+ { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
+ { IVPU_HW_IP_40XX, "vpu_40xx.bin" },
+ { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
++ { IVPU_HW_IP_50XX, "vpu_50xx.bin" },
++ { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" },
+ };
+
+ /* Production fw_names from the table above */
+ MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin");
+ MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin");
++MODULE_FIRMWARE("intel/vpu/vpu_50xx_v0.0.bin");
+
+ static int ivpu_fw_request(struct ivpu_device *vdev)
+ {
--- /dev/null
+From 88bdd1644ca28d48591b2a1e6e8b8c2b13f4bd3f Mon Sep 17 00:00:00 2001
+From: Karol Wachowski <karol.wachowski@intel.com>
+Date: Fri, 4 Oct 2024 18:25:05 +0200
+Subject: accel/ivpu: Update power island delays
+
+From: Karol Wachowski <karol.wachowski@intel.com>
+
+commit 88bdd1644ca28d48591b2a1e6e8b8c2b13f4bd3f upstream.
+
+Apply Hardware Architecture Specification compatible delays
+for main island power delivery for 50xx and above.
+
+Signed-off-by: Karol Wachowski <karol.wachowski@intel.com>
+Signed-off-by: Maciej Falkowski <maciej.falkowski@linux.intel.com>
+Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20241004162505.1695605-3-maciej.falkowski@linux.intel.com
+Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/accel/ivpu/ivpu_hw_40xx_reg.h | 2 +
+ drivers/accel/ivpu/ivpu_hw_ip.c | 49 ++++++++++++++++++++++------------
+ 2 files changed, 34 insertions(+), 17 deletions(-)
+
+--- a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
++++ b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
+@@ -115,6 +115,8 @@
+
+ #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u
+ #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0)
++#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK GENMASK(15, 8)
++#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK GENMASK(23, 16)
+
+ #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu
+ #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)
+--- a/drivers/accel/ivpu/ivpu_hw_ip.c
++++ b/drivers/accel/ivpu/ivpu_hw_ip.c
+@@ -8,15 +8,12 @@
+ #include "ivpu_hw.h"
+ #include "ivpu_hw_37xx_reg.h"
+ #include "ivpu_hw_40xx_reg.h"
++#include "ivpu_hw_btrs.h"
+ #include "ivpu_hw_ip.h"
+ #include "ivpu_hw_reg_io.h"
+ #include "ivpu_mmu.h"
+ #include "ivpu_pm.h"
+
+-#define PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT 0
+-#define PWR_ISLAND_EN_POST_DLY_FREQ_HIGH 18
+-#define PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT 3
+-#define PWR_ISLAND_STATUS_DLY_FREQ_HIGH 46
+ #define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
+
+ #define TIM_SAFE_ENABLE 0xf1d0dead
+@@ -268,20 +265,15 @@ void ivpu_hw_ip_idle_gen_disable(struct
+ idle_gen_drive_40xx(vdev, false);
+ }
+
+-static void pwr_island_delay_set_50xx(struct ivpu_device *vdev)
++static void
++pwr_island_delay_set_50xx(struct ivpu_device *vdev, u32 post, u32 post1, u32 post2, u32 status)
+ {
+- u32 val, post, status;
+-
+- if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) {
+- post = PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT;
+- status = PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT;
+- } else {
+- post = PWR_ISLAND_EN_POST_DLY_FREQ_HIGH;
+- status = PWR_ISLAND_STATUS_DLY_FREQ_HIGH;
+- }
++ u32 val;
+
+ val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);
+ val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val);
++ val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val);
++ val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val);
+ REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val);
+
+ val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);
+@@ -686,13 +678,36 @@ static void dpu_active_drive_37xx(struct
+ REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
+ }
+
++static void pwr_island_delay_set(struct ivpu_device *vdev)
++{
++ bool high = vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH;
++ u32 post, post1, post2, status;
++
++ if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX)
++ return;
++
++ switch (ivpu_device_id(vdev)) {
++ case PCI_DEVICE_ID_PTL_P:
++ post = high ? 18 : 0;
++ post1 = 0;
++ post2 = 0;
++ status = high ? 46 : 3;
++ break;
++
++ default:
++ dump_stack();
++ ivpu_err(vdev, "Unknown device ID\n");
++ return;
++ }
++
++ pwr_island_delay_set_50xx(vdev, post, post1, post2, status);
++}
++
+ int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev)
+ {
+ int ret;
+
+- if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_50XX)
+- pwr_island_delay_set_50xx(vdev);
+-
++ pwr_island_delay_set(vdev);
+ pwr_island_enable(vdev);
+
+ ret = wait_for_pwr_island_status(vdev, 0x1);
--- /dev/null
+From 26064d3e2b4d9a14df1072980e558c636fb023ea Mon Sep 17 00:00:00 2001
+From: Ming Lei <ming.lei@redhat.com>
+Date: Wed, 12 Mar 2025 22:51:36 +0800
+Subject: block: fix adding folio to bio
+
+From: Ming Lei <ming.lei@redhat.com>
+
+commit 26064d3e2b4d9a14df1072980e558c636fb023ea upstream.
+
+>4GB folio is possible on some ARCHs, such as aarch64, 16GB hugepage
+is supported, then 'offset' of folio can't be held in 'unsigned int',
+cause warning in bio_add_folio_nofail() and IO failure.
+
+Fix it by adjusting 'page' & trimming 'offset' so that `->bi_offset` won't
+be overflow, and folio can be added to bio successfully.
+
+Fixes: ed9832bc08db ("block: introduce folio awareness and add a bigger size from folio")
+Cc: Kundan Kumar <kundan.kumar@samsung.com>
+Cc: Matthew Wilcox (Oracle) <willy@infradead.org>
+Cc: Christoph Hellwig <hch@lst.de>
+Cc: Luis Chamberlain <mcgrof@kernel.org>
+Cc: Gavin Shan <gshan@redhat.com>
+Signed-off-by: Ming Lei <ming.lei@redhat.com>
+Reviewed-by: Matthew Wilcox (Oracle) <willy@infradead.org>
+Link: https://lore.kernel.org/r/20250312145136.2891229-1-ming.lei@redhat.com
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+[ The follow-up fix fbecd731de05 ("xfs: fix zoned GC data corruption due to
+ wrong bv_offset") addresses issues in the file fs/xfs/xfs_zone_gc.c. This
+ file was first introduced in version v6.15-rc1. So don't backport the follow
+ up fix to 6.12.y. ]
+Signed-off-by: Alva Lan <alvalan9@foxmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ block/bio.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/block/bio.c
++++ b/block/bio.c
+@@ -1156,9 +1156,10 @@ EXPORT_SYMBOL(bio_add_page);
+ void bio_add_folio_nofail(struct bio *bio, struct folio *folio, size_t len,
+ size_t off)
+ {
++ unsigned long nr = off / PAGE_SIZE;
++
+ WARN_ON_ONCE(len > UINT_MAX);
+- WARN_ON_ONCE(off > UINT_MAX);
+- __bio_add_page(bio, &folio->page, len, off);
++ __bio_add_page(bio, folio_page(folio, nr), len, off % PAGE_SIZE);
+ }
+ EXPORT_SYMBOL_GPL(bio_add_folio_nofail);
+
+@@ -1179,9 +1180,11 @@ EXPORT_SYMBOL_GPL(bio_add_folio_nofail);
+ bool bio_add_folio(struct bio *bio, struct folio *folio, size_t len,
+ size_t off)
+ {
+- if (len > UINT_MAX || off > UINT_MAX)
++ unsigned long nr = off / PAGE_SIZE;
++
++ if (len > UINT_MAX)
+ return false;
+- return bio_add_page(bio, &folio->page, len, off) > 0;
++ return bio_add_page(bio, folio_page(folio, nr), len, off % PAGE_SIZE) > 0;
+ }
+ EXPORT_SYMBOL(bio_add_folio);
+
--- /dev/null
+From 7447990137bf06b2aeecad9c6081e01a9f47f2aa Mon Sep 17 00:00:00 2001
+From: Ajay Agarwal <ajayagarwal@google.com>
+Date: Mon, 7 Oct 2024 08:59:17 +0530
+Subject: PCI/ASPM: Disable L1 before disabling L1 PM Substates
+
+From: Ajay Agarwal <ajayagarwal@google.com>
+
+commit 7447990137bf06b2aeecad9c6081e01a9f47f2aa upstream.
+
+PCIe r6.2, sec 5.5.4, requires that:
+
+ If setting either or both of the enable bits for ASPM L1 PM Substates,
+ both ports must be configured as described in this section while ASPM L1
+ is disabled.
+
+Previously, pcie_config_aspm_l1ss() assumed that "setting enable bits"
+meant "setting them to 1", and it configured L1SS as follows:
+
+ - Clear L1SS enable bits
+ - Disable L1
+ - Configure L1SS enable bits as required
+ - Enable L1 if required
+
+With this sequence, when disabling L1SS on an ARM A-core with a Synopsys
+DesignWare PCIe core, the CPU occasionally hangs when reading
+PCI_L1SS_CTL1, leading to a reboot when the CPU watchdog expires.
+
+Move the L1 disable to the caller (pcie_config_aspm_link(), where L1 was
+already enabled) so L1 is always disabled while updating the L1SS bits:
+
+ - Disable L1
+ - Clear L1SS enable bits
+ - Configure L1SS enable bits as required
+ - Enable L1 if required
+
+Change pcie_aspm_cap_init() similarly.
+
+Link: https://lore.kernel.org/r/20241007032917.872262-1-ajayagarwal@google.com
+Signed-off-by: Ajay Agarwal <ajayagarwal@google.com>
+[bhelgaas: comments, commit log, compute L1SS setting before config access]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Tested-by: Johnny-CC Chang <Johnny-CC.Chang@mediatek.com>
+Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/pcie/aspm.c | 92 ++++++++++++++++++++++++++----------------------
+ 1 file changed, 50 insertions(+), 42 deletions(-)
+
+--- a/drivers/pci/pcie/aspm.c
++++ b/drivers/pci/pcie/aspm.c
+@@ -805,6 +805,15 @@ static void pcie_aspm_cap_init(struct pc
+ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
+ pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
+
++ /* Disable L0s/L1 before updating L1SS config */
++ if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
++ FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
++ pcie_capability_write_word(child, PCI_EXP_LNKCTL,
++ child_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
++ pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
++ parent_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
++ }
++
+ /*
+ * Setup L0s state
+ *
+@@ -829,6 +838,13 @@ static void pcie_aspm_cap_init(struct pc
+
+ aspm_l1ss_init(link);
+
++ /* Restore L0s/L1 if they were enabled */
++ if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
++ FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
++ pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_lnkctl);
++ pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_lnkctl);
++ }
++
+ /* Save default state */
+ link->aspm_default = link->aspm_enabled;
+
+@@ -845,25 +861,28 @@ static void pcie_aspm_cap_init(struct pc
+ }
+ }
+
+-/* Configure the ASPM L1 substates */
++/* Configure the ASPM L1 substates. Caller must disable L1 first. */
+ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
+ {
+- u32 val, enable_req;
++ u32 val;
+ struct pci_dev *child = link->downstream, *parent = link->pdev;
+
+- enable_req = (link->aspm_enabled ^ state) & state;
++ val = 0;
++ if (state & PCIE_LINK_STATE_L1_1)
++ val |= PCI_L1SS_CTL1_ASPM_L1_1;
++ if (state & PCIE_LINK_STATE_L1_2)
++ val |= PCI_L1SS_CTL1_ASPM_L1_2;
++ if (state & PCIE_LINK_STATE_L1_1_PCIPM)
++ val |= PCI_L1SS_CTL1_PCIPM_L1_1;
++ if (state & PCIE_LINK_STATE_L1_2_PCIPM)
++ val |= PCI_L1SS_CTL1_PCIPM_L1_2;
+
+ /*
+- * Here are the rules specified in the PCIe spec for enabling L1SS:
+- * - When enabling L1.x, enable bit at parent first, then at child
+- * - When disabling L1.x, disable bit at child first, then at parent
+- * - When enabling ASPM L1.x, need to disable L1
+- * (at child followed by parent).
+- * - The ASPM/PCIPM L1.2 must be disabled while programming timing
++ * PCIe r6.2, sec 5.5.4, rules for enabling L1 PM Substates:
++ * - Clear L1.x enable bits at child first, then at parent
++ * - Set L1.x enable bits at parent first, then at child
++ * - ASPM/PCIPM L1.2 must be disabled while programming timing
+ * parameters
+- *
+- * To keep it simple, disable all L1SS bits first, and later enable
+- * what is needed.
+ */
+
+ /* Disable all L1 substates */
+@@ -871,26 +890,6 @@ static void pcie_config_aspm_l1ss(struct
+ PCI_L1SS_CTL1_L1SS_MASK, 0);
+ pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_L1SS_MASK, 0);
+- /*
+- * If needed, disable L1, and it gets enabled later
+- * in pcie_config_aspm_link().
+- */
+- if (enable_req & (PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2)) {
+- pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
+- PCI_EXP_LNKCTL_ASPM_L1);
+- pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
+- PCI_EXP_LNKCTL_ASPM_L1);
+- }
+-
+- val = 0;
+- if (state & PCIE_LINK_STATE_L1_1)
+- val |= PCI_L1SS_CTL1_ASPM_L1_1;
+- if (state & PCIE_LINK_STATE_L1_2)
+- val |= PCI_L1SS_CTL1_ASPM_L1_2;
+- if (state & PCIE_LINK_STATE_L1_1_PCIPM)
+- val |= PCI_L1SS_CTL1_PCIPM_L1_1;
+- if (state & PCIE_LINK_STATE_L1_2_PCIPM)
+- val |= PCI_L1SS_CTL1_PCIPM_L1_2;
+
+ /* Enable what we need to enable */
+ pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+@@ -937,21 +936,30 @@ static void pcie_config_aspm_link(struct
+ dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
+ }
+
++ /*
++ * Per PCIe r6.2, sec 5.5.4, setting either or both of the enable
++ * bits for ASPM L1 PM Substates must be done while ASPM L1 is
++ * disabled. Disable L1 here and apply new configuration after L1SS
++ * configuration has been completed.
++ *
++ * Per sec 7.5.3.7, when disabling ASPM L1, software must disable
++ * it in the Downstream component prior to disabling it in the
++ * Upstream component, and ASPM L1 must be enabled in the Upstream
++ * component prior to enabling it in the Downstream component.
++ *
++ * Sec 7.5.3.7 also recommends programming the same ASPM Control
++ * value for all functions of a multi-function device.
++ */
++ list_for_each_entry(child, &linkbus->devices, bus_list)
++ pcie_config_aspm_dev(child, 0);
++ pcie_config_aspm_dev(parent, 0);
++
+ if (link->aspm_capable & PCIE_LINK_STATE_L1SS)
+ pcie_config_aspm_l1ss(link, state);
+
+- /*
+- * Spec 2.0 suggests all functions should be configured the
+- * same setting for ASPM. Enabling ASPM L1 should be done in
+- * upstream component first and then downstream, and vice
+- * versa for disabling ASPM L1. Spec doesn't mention L0S.
+- */
+- if (state & PCIE_LINK_STATE_L1)
+- pcie_config_aspm_dev(parent, upstream);
++ pcie_config_aspm_dev(parent, upstream);
+ list_for_each_entry(child, &linkbus->devices, bus_list)
+ pcie_config_aspm_dev(child, dwstream);
+- if (!(state & PCIE_LINK_STATE_L1))
+- pcie_config_aspm_dev(parent, upstream);
+
+ link->aspm_enabled = state;
+
--- /dev/null
+From fe9f5f96cfe8b82d0f24cbfa93718925560f4f8d Mon Sep 17 00:00:00 2001
+From: Alexandre Mergnat <amergnat@baylibre.com>
+Date: Mon, 28 Apr 2025 12:06:48 +0200
+Subject: rtc: Fix offset calculation for .start_secs < 0
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alexandre Mergnat <amergnat@baylibre.com>
+
+commit fe9f5f96cfe8b82d0f24cbfa93718925560f4f8d upstream.
+
+The comparison
+
+ rtc->start_secs > rtc->range_max
+
+has a signed left-hand side and an unsigned right-hand side.
+So the comparison might become true for negative start_secs which is
+interpreted as a (possibly very large) positive value.
+
+As a negative value can never be bigger than an unsigned value
+the correct representation of the (mathematical) comparison
+
+ rtc->start_secs > rtc->range_max
+
+in C is:
+
+ rtc->start_secs >= 0 && rtc->start_secs > rtc->range_max
+
+Use that to fix the offset calculation currently used in the
+rtc-mt6397 driver.
+
+Fixes: 989515647e783 ("rtc: Add one offset seconds to expand RTC range")
+Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
+Link: https://lore.kernel.org/r/20250428-enable-rtc-v4-2-2b2f7e3f9349@baylibre.com
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/rtc/class.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/rtc/class.c
++++ b/drivers/rtc/class.c
+@@ -327,7 +327,7 @@ static void rtc_device_get_offset(struct
+ *
+ * Otherwise the offset seconds should be 0.
+ */
+- if (rtc->start_secs > rtc->range_max ||
++ if ((rtc->start_secs >= 0 && rtc->start_secs > rtc->range_max) ||
+ rtc->start_secs + range_secs - 1 < rtc->range_min)
+ rtc->offset_secs = rtc->start_secs - rtc->range_min;
+ else if (rtc->start_secs > rtc->range_min)
--- /dev/null
+From 7df4cfef8b351fec3156160bedfc7d6d29de4cce Mon Sep 17 00:00:00 2001
+From: Alexandre Mergnat <amergnat@baylibre.com>
+Date: Mon, 28 Apr 2025 12:06:47 +0200
+Subject: rtc: Make rtc_time64_to_tm() support dates before 1970
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alexandre Mergnat <amergnat@baylibre.com>
+
+commit 7df4cfef8b351fec3156160bedfc7d6d29de4cce upstream.
+
+Conversion of dates before 1970 is still relevant today because these
+dates are reused on some hardwares to store dates bigger than the
+maximal date that is representable in the device's native format.
+This prominently and very soon affects the hardware covered by the
+rtc-mt6397 driver that can only natively store dates in the interval
+1900-01-01 up to 2027-12-31. So to store the date 2028-01-01 00:00:00
+to such a device, rtc_time64_to_tm() must do the right thing for
+time=-2208988800.
+
+Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
+Link: https://lore.kernel.org/r/20250428-enable-rtc-v4-1-2b2f7e3f9349@baylibre.com
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/rtc/lib.c | 24 +++++++++++++++++++-----
+ 1 file changed, 19 insertions(+), 5 deletions(-)
+
+--- a/drivers/rtc/lib.c
++++ b/drivers/rtc/lib.c
+@@ -46,24 +46,38 @@ EXPORT_SYMBOL(rtc_year_days);
+ * rtc_time64_to_tm - converts time64_t to rtc_time.
+ *
+ * @time: The number of seconds since 01-01-1970 00:00:00.
+- * (Must be positive.)
++ * Works for values since at least 1900
+ * @tm: Pointer to the struct rtc_time.
+ */
+ void rtc_time64_to_tm(time64_t time, struct rtc_time *tm)
+ {
+- unsigned int secs;
+- int days;
++ int days, secs;
+
+ u64 u64tmp;
+ u32 u32tmp, udays, century, day_of_century, year_of_century, year,
+ day_of_year, month, day;
+ bool is_Jan_or_Feb, is_leap_year;
+
+- /* time must be positive */
++ /*
++ * Get days and seconds while preserving the sign to
++ * handle negative time values (dates before 1970-01-01)
++ */
+ days = div_s64_rem(time, 86400, &secs);
+
++ /*
++ * We need 0 <= secs < 86400 which isn't given for negative
++ * values of time. Fixup accordingly.
++ */
++ if (secs < 0) {
++ days -= 1;
++ secs += 86400;
++ }
++
+ /* day of the week, 1970-01-01 was a Thursday */
+ tm->tm_wday = (days + 4) % 7;
++ /* Ensure tm_wday is always positive */
++ if (tm->tm_wday < 0)
++ tm->tm_wday += 7;
+
+ /*
+ * The following algorithm is, basically, Proposition 6.3 of Neri
+@@ -93,7 +107,7 @@ void rtc_time64_to_tm(time64_t time, str
+ * thus, is slightly different from [1].
+ */
+
+- udays = ((u32) days) + 719468;
++ udays = days + 719468;
+
+ u32tmp = 4 * udays + 3;
+ century = u32tmp / 146097;
pinctrl-armada-37xx-set-gpio-output-value-before-setting-direction.patch
acpi-cpufreq-fix-nominal_freq-units-to-khz-in-get_max_boost_ratio.patch
documentation-acpi-use-all-string-data-node-references.patch
+rtc-make-rtc_time64_to_tm-support-dates-before-1970.patch
+rtc-fix-offset-calculation-for-.start_secs-0.patch
+accel-ivpu-add-initial-panther-lake-support.patch
+accel-ivpu-update-power-island-delays.patch
+pci-aspm-disable-l1-before-disabling-l1-pm-substates.patch
+block-fix-adding-folio-to-bio.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
