RISC-V: Refine the testcase of vector SAT_SUB

Take scan-assembler-times for vssub insn check instead of function body,
as we only care about if we can generate the fixed point insn vssub.

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Remove
	func body check and take scan asm times instead.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
index bd8fbc192b43883d4c1d1b344a4ad16efe982450..b989cb6c1e1d1177cdc7d99dd38ee98f820893f2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
index 52c2a68688166220e43ef8538224b675e25e6106..b2fc9887b5a43b5e42b3bb3ce342e43fc1c5fadb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
index 37fde86fe31d2314a15eff6b58ac20ef87b3be4b..944b197f21f2c809beb0af814374bce1c31de2a6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
index c6f33cff65036b943960a7bf13798c3f30aa707d..862fd41176f01157e64d4e4632452f33403a333a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
index 426220969d2cb8c1aa9d7fbbd3c5643ab86fc80e..edadbf0d04686d06168f26a71c58b9e7c06f4298 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
index 9d16b838195a2d2970d4dcbe361efd28cf83a488..d3eadae0cb6b2d0d4ed29a78171370b850098860 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
index f673839f0e767ef794e0159a8978a8d03c4da2aa..b9f61fd02b17dcadb4ac3a45f678093a81b62687 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
index cd9af177e941e6f26e6415cacef2ddc8cd929300..8171a3e9fcc954eb22e665af73165184ad09c37a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
index f74f0750932e2216807462cc6c1d43f2f703d880..4e1f65500e1709309b2b007ffd5d858e91386b0f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
index 0f8f909c52596a4cf0c65b79f738d73da9741c46..d259675c961b8057bd4ccec077d6bda60d272cc5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
index 9b627e6a34256d67af3348c1d34cfeb30ebc3c15..19aaa7e2a87e3ae671dc2d0ffc0b42a52ce25d33 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
index d2d0c04935ba3a056a8c38c293eb43be1c603a35..5ed44d9fe707424286da38c050b9fe55d05e7283 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
index cab2938625745d14381a47df7bdda924c52ff80d..ea95a372a5575c2495ae0a04f534647884a3093f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
index 78261081fe3a52080bc5a900a01753cd2b7de2d5..9fee7955046700756f0e05f507394431f53294e0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
index 04a2c58e2422357c807b6113d82fa698118e3753..de8defcc641e5b5f6c82657ce88fd6ce9d575cba 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
index eb7dac69989ea368820a5f2a1b3427a6add90dff..aed21c7bab782a9a83ea1bedd512f04c02c12839 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
index 6a1551122a9f40078442557c392fe3ce47b2a7fd..8bfe35d82560145c960e11184c1e855a24c2a780 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
index 4611ac7b09b9898b381de7a201f5e76353e119b1..7554929823f8fac0a90931d92a5cb1ad0d0b47ff 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
index ee0853d6f71b8aeb937ca39c97e6c1c8528e11c4..7994bbbcdc5a8a517011c029c65d7a50203baffb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
index 7af569d921939f6417c2a9e54d75865429dbb80f..2f2665dd2b87053d6359fbed0efd4f11fad3f21e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
index 70ae92983562cf1a19221add4ffe360d4e6e41e6..0c181e1dd4d3353db2a75645ac6665675ec61448 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
index 1ff020ff878bb2abdd075f382415373747473ec8..b1fd6f9dae496285f08361bf2684233f8948144e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
index 3dde5f27f4dc37b7ec71c23b8da38d540ba1a68b..e67da174badb440c498f089e54020e5fe94d403a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
index b658c2261990cea74b21d2787765b07f212e9b9c..ca187271e85ebb8c6705d987a85d576906657119 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
index df1435dbb3e38274ad416947f4cbc96327a842f6..203776e9d0d0eb9f2e80fb73e3ce05a7164ddd56 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
index 77e332345752120c73e0e9e6d505d9323809bce0..6aed87903e15225de92253ff9026dc92d38afb08 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
index 4885dda08ae61a3d00ae1ec8d3802174a2db4ef3..b5caadb3e4b137742d2dc36a6e6eb04b740560ae 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
index 33d69e193a4d949ff829fe1c9d3a6ee3a84d4e74..eaa7b33d410da814ff67d7f9dc6047efbeda75b4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
index a050e0df8c3fc08cb5c7ff970ef20fc35b4358f1..f885b2c2237e98b38ee4cd715cb3eec337cebebd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
index 0abb6e0a86c6e2dd73620119d2790830520562f4..4f5ab41905851dc438cbf621b237b61a0ec58090 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
index f40f56da9d92c569ca3d876c73a80bbaeec081ac..aa90e04f33d50b768f48df14bfd6f70992867817 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
index 7031f16bf5ea37b51c852658037c957534d522a0..becaa6b50407369462719dd47e43472a416f7194 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
index 0cc1298fa9a700adfe8fa666889f572484e7036d..e104793b9a71b7dcb3447801b0527134b8908874 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
index 00a671983f7117e0337a70e0ae2050b3ceb977ad..0efdf6581812993e43962c28c0ce494540728cd2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
index 2aba688eb975f03c3de62ef1183da255c4a45c48..c73b98e73a88e76cf8921ad0b1bba784cf6e1856 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
index 86cd920bd0c616132fb73a1b37b563f3823e0756..6c42573830c70378a05afce5de41c21f1330de9a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
index d8880e55f9517a792ee4b7cdf5d5f7809bfdb0c1..cde246527117bd39760f7732a2b83fc10d3a3a12 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
index 6ba1d1bb12af7c5c417c25c8a82eaf497dc671b8..5399519658601f4f3021a7d759348b7460d40d41 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
index b3e40ed31b39c5f4479474a3be89da6a20d8a8d7..ade479ec758b3d7f38e17e6565c60000f1462137 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
index ffc68e7b6dcef9deb536388b41e5272fb0b06224..6221f18a1e716e5ee1d98989e866cd85c81bd9d2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
index 1386f52d020a01dd568119d91116d44b0b2aea0b..674206bea37c42055ec274bc4c9a0c1c9e7fc2db 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -1,22 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_trunc_uint8_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
-** ...
-** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
index 959e2e1a29375d489a7dd47055390a7862171945..32e828c5c744169a58400c5576c7d2b508c06ebf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -1,22 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_trunc_uint16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
index 769e0af309ed5e64e959e41f4f57ee841f3dbc92..72afd0872d2de328ade9494c6c3a8e9ff4721e61 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -1,22 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_trunc_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
-** ...
-** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
index 29b32f34b46cdb50ab9db2b7b12a209bb2e9b1b7..16ff0c63e5a71cadd7bfa62e4b592c27d091c81f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
@@ -1,18 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_uint32_t_fmt_zip:
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vrgather\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */