drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes

drm_panic draws in linear framebuffer, so it's easier to re-use the
current framebuffer, and disable tiling in the panic handler, to show
the panic screen.
This assumes that the alignment restriction is always smaller in
linear than in tiled.
It also assumes that the linear framebuffer size is always smaller
than the tiled.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250624091501.257661-4-jfalempe@redhat.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ac84558006c7c53ed554da8ffe09a25b91b6924d..e7e35fd4bdc375020d7d012d5bb04444f0044741 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -905,6 +905,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = {
        .format_mod_supported_async = intel_plane_format_mod_supported_async,
 };
 
+static void i9xx_disable_tiling(struct intel_plane *plane)
+{
+       struct intel_display *display = to_intel_display(plane);
+       enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+       u32 dspcntr;
+       u32 reg;
+
+       dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));
+       dspcntr &= ~DISP_TILED;
+       intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
+
+       if (DISPLAY_VER(display) >= 4) {
+               reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));
+               intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg);
+
+       } else {
+               reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));
+               intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg);
+       }
+}
+
 struct intel_plane *
 intel_primary_plane_create(struct intel_display *display, enum pipe pipe)
 {
@@ -1047,6 +1068,8 @@ intel_primary_plane_create(struct intel_display *display, enum pipe pipe)
                }
        }
 
+       plane->disable_tiling = i9xx_disable_tiling;
+
        modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);
 
        if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 30c7315fc25e3d757db166f9a837376e1c45429c..6cd8eb26f85890c1319644736721d7583d12b10a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1521,6 +1521,8 @@ struct intel_plane {
                           bool async_flip);
        void (*enable_flip_done)(struct intel_plane *plane);
        void (*disable_flip_done)(struct intel_plane *plane);
+       /* For drm_panic */
+       void (*disable_tiling)(struct intel_plane *plane);
 };
 
 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)