net: liquidio: Remove unused cn23xx_dump_pf_initialized_regs

cn23xx_dump_pf_initialized_regs() was added in 2016's commit
72c0091293c0 ("liquidio: CN23XX device init and sriov config")

but hasn't been used.

Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20241009003841.254853-1-linux@treblig.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
index b3c81a2e9d4643bb818f38069c9bfefe5ea290f0..9ad49aea2673b6a51aac1269b6e0adb0459a7c68 100644 (file)
--- a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
+++ b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
@@ -36,175 +36,6 @@
  */
 #define CN23XX_INPUT_JABBER 64600
 
-void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct)
-{
-       int i = 0;
-       u32 regval = 0;
-       struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
-
-       /*In cn23xx_soft_reset*/
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%llx\n",
-               "CN23XX_WIN_WR_MASK_REG", CVM_CAST64(CN23XX_WIN_WR_MASK_REG),
-               CVM_CAST64(octeon_read_csr64(oct, CN23XX_WIN_WR_MASK_REG)));
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_SLI_SCRATCH1", CVM_CAST64(CN23XX_SLI_SCRATCH1),
-               CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)));
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_RST_SOFT_RST", CN23XX_RST_SOFT_RST,
-               lio_pci_readq(oct, CN23XX_RST_SOFT_RST));
-
-       /*In cn23xx_set_dpi_regs*/
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_DPI_DMA_CONTROL", CN23XX_DPI_DMA_CONTROL,
-               lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL));
-
-       for (i = 0; i < 6; i++) {
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_DPI_DMA_ENG_ENB", i,
-                       CN23XX_DPI_DMA_ENG_ENB(i),
-                       lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i)));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_DPI_DMA_ENG_BUF", i,
-                       CN23XX_DPI_DMA_ENG_BUF(i),
-                       lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i)));
-       }
-
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", "CN23XX_DPI_CTL",
-               CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL));
-
-       /*In cn23xx_setup_pcie_mps and cn23xx_setup_pcie_mrrs */
-       pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_CONFIG_PCIE_DEVCTL",
-               CVM_CAST64(CN23XX_CONFIG_PCIE_DEVCTL), CVM_CAST64(regval));
-
-       dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-               "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port,
-               CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port),
-               lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port)));
-
-       /*In cn23xx_specific_regs_setup */
-       dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-               "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port,
-               CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)),
-               CVM_CAST64(octeon_read_csr64(
-                       oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port))));
-
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_SLI_RING_RST", CVM_CAST64(CN23XX_SLI_PKT_IOQ_RING_RST),
-               (u64)octeon_read_csr64(oct, CN23XX_SLI_PKT_IOQ_RING_RST));
-
-       /*In cn23xx_setup_global_mac_regs*/
-       for (i = 0; i < CN23XX_MAX_MACS; i++) {
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_PKT_MAC_RINFO64", i,
-                       CVM_CAST64(CN23XX_SLI_PKT_MAC_RINFO64(i, oct->pf_num)),
-                       CVM_CAST64(octeon_read_csr64
-                               (oct, CN23XX_SLI_PKT_MAC_RINFO64
-                                       (i, oct->pf_num))));
-       }
-
-       /*In cn23xx_setup_global_input_regs*/
-       for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_IQ_PKT_CONTROL64", i,
-                       CVM_CAST64(CN23XX_SLI_IQ_PKT_CONTROL64(i)),
-                       CVM_CAST64(octeon_read_csr64
-                               (oct, CN23XX_SLI_IQ_PKT_CONTROL64(i))));
-       }
-
-       /*In cn23xx_setup_global_output_regs*/
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_SLI_OQ_WMARK", CVM_CAST64(CN23XX_SLI_OQ_WMARK),
-               CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_OQ_WMARK)));
-
-       for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_PKT_CONTROL", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_PKT_CONTROL(i)),
-                       CVM_CAST64(octeon_read_csr(
-                               oct, CN23XX_SLI_OQ_PKT_CONTROL(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_PKT_INT_LEVELS", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_PKT_INT_LEVELS(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(i))));
-       }
-
-       /*In cn23xx_enable_interrupt and cn23xx_disable_interrupt*/
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "cn23xx->intr_enb_reg64",
-               CVM_CAST64((long)(cn23xx->intr_enb_reg64)),
-               CVM_CAST64(readq(cn23xx->intr_enb_reg64)));
-
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "cn23xx->intr_sum_reg64",
-               CVM_CAST64((long)(cn23xx->intr_sum_reg64)),
-               CVM_CAST64(readq(cn23xx->intr_sum_reg64)));
-
-       /*In cn23xx_setup_iq_regs*/
-       for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_IQ_BASE_ADDR64", i,
-                       CVM_CAST64(CN23XX_SLI_IQ_BASE_ADDR64(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_IQ_BASE_ADDR64(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_IQ_SIZE", i,
-                       CVM_CAST64(CN23XX_SLI_IQ_SIZE(i)),
-                       CVM_CAST64(octeon_read_csr
-                               (oct, CN23XX_SLI_IQ_SIZE(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_IQ_DOORBELL", i,
-                       CVM_CAST64(CN23XX_SLI_IQ_DOORBELL(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_IQ_DOORBELL(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_IQ_INSTR_COUNT64", i,
-                       CVM_CAST64(CN23XX_SLI_IQ_INSTR_COUNT64(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_IQ_INSTR_COUNT64(i))));
-       }
-
-       /*In cn23xx_setup_oq_regs*/
-       for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_BASE_ADDR64", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_BASE_ADDR64(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_OQ_BASE_ADDR64(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_SIZE", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_SIZE(i)),
-                       CVM_CAST64(octeon_read_csr
-                               (oct, CN23XX_SLI_OQ_SIZE(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_BUFF_INFO_SIZE", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_BUFF_INFO_SIZE(i)),
-                       CVM_CAST64(octeon_read_csr(
-                               oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_PKTS_SENT", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_PKTS_SENT(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_OQ_PKTS_SENT(i))));
-               dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
-                       "CN23XX_SLI_OQ_PKTS_CREDIT", i,
-                       CVM_CAST64(CN23XX_SLI_OQ_PKTS_CREDIT(i)),
-                       CVM_CAST64(octeon_read_csr64(
-                               oct, CN23XX_SLI_OQ_PKTS_CREDIT(i))));
-       }
-
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_SLI_PKT_TIME_INT",
-               CVM_CAST64(CN23XX_SLI_PKT_TIME_INT),
-               CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_TIME_INT)));
-       dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
-               "CN23XX_SLI_PKT_CNT_INT",
-               CVM_CAST64(CN23XX_SLI_PKT_CNT_INT),
-               CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT)));
-}
-
 static int cn23xx_pf_soft_reset(struct octeon_device *oct)
 {
        octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);

diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.h b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.h
index e6f31d0d5c0b66e99675109b073f301f06fdfaaa..234b96b4f48870d5fbf671ff11cc2cb18c38d754 100644 (file)
--- a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.h
+++ b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.h
@@ -59,8 +59,6 @@ int validate_cn23xx_pf_config_info(struct octeon_device *oct,
 
 u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
 
-void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct);
-
 int cn23xx_sriov_config(struct octeon_device *oct);
 
 int cn23xx_fw_loaded(struct octeon_device *oct);