dmaengine: qcom: bam_dma: Add support for BAM v2.0.0

Add register offset table entry for bam v2.0.0 version found on
kaanapali.

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260514-knp_qce-v2-2-890e3372eef8@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 19116295f8325767a0d97a7848077885b118241c..1bb26af0405f3a16f97e0d4b86c945c252d97f57 100644 (file)
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -199,6 +199,35 @@ static const struct reg_offset_data bam_v1_7_reg_info[] = {
        [BAM_P_FIFO_SIZES]      = { 0x13820, 0x00, 0x1000, 0x00 },
 };
 
+static const struct reg_offset_data bam_v2_0_reg_info[] = {
+       [BAM_CTRL]              = { 0x0000, 0x00, 0x00, 0x00 },
+       [BAM_REVISION]          = { 0x1000, 0x00, 0x00, 0x00 },
+       [BAM_NUM_PIPES]         = { 0x1008, 0x00, 0x00, 0x00 },
+       [BAM_DESC_CNT_TRSHLD]   = { 0x0008, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_SRCS]          = { 0x3010, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_SRCS_MSK]      = { 0x3014, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_SRCS_UNMASKED] = { 0x3018, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_STTS]          = { 0x0014, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_CLR]           = { 0x0018, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_EN]            = { 0x001C, 0x00, 0x00, 0x00 },
+       [BAM_CNFG_BITS]         = { 0x007C, 0x00, 0x00, 0x00 },
+       [BAM_IRQ_SRCS_EE]       = { 0x3000, 0x00, 0x00, 0x1000 },
+       [BAM_IRQ_SRCS_MSK_EE]   = { 0x3004, 0x00, 0x00, 0x1000 },
+       [BAM_P_CTRL]            = { 0xC000, 0x1000, 0x00, 0x00 },
+       [BAM_P_RST]             = { 0xC004, 0x1000, 0x00, 0x00 },
+       [BAM_P_HALT]            = { 0xC008, 0x1000, 0x00, 0x00 },
+       [BAM_P_IRQ_STTS]        = { 0xC010, 0x1000, 0x00, 0x00 },
+       [BAM_P_IRQ_CLR]         = { 0xC014, 0x1000, 0x00, 0x00 },
+       [BAM_P_IRQ_EN]          = { 0xC018, 0x1000, 0x00, 0x00 },
+       [BAM_P_EVNT_DEST_ADDR]  = { 0xC82C, 0x00, 0x1000, 0x00 },
+       [BAM_P_EVNT_REG]        = { 0xC818, 0x00, 0x1000, 0x00 },
+       [BAM_P_SW_OFSTS]        = { 0xC800, 0x00, 0x1000, 0x00 },
+       [BAM_P_DATA_FIFO_ADDR]  = { 0xC824, 0x00, 0x1000, 0x00 },
+       [BAM_P_DESC_FIFO_ADDR]  = { 0xC81C, 0x00, 0x1000, 0x00 },
+       [BAM_P_EVNT_GEN_TRSHLD] = { 0xC828, 0x00, 0x1000, 0x00 },
+       [BAM_P_FIFO_SIZES]      = { 0xC820, 0x00, 0x1000, 0x00 },
+};
+
 /* BAM CTRL */
 #define BAM_SW_RST                     BIT(0)
 #define BAM_EN                         BIT(1)
@@ -1208,6 +1237,7 @@ static const struct of_device_id bam_of_match[] = {
        { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
        { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
        { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info },
+       { .compatible = "qcom,bam-v2.0.0", .data = &bam_v2_0_reg_info },
        {}
 };