re PR target/20814 (ICE in extract_insn for test vmx/varargs-1.c)

        PR target/20814
        * config/rs6000/predicates.md (altivec_register_operand): Accept
        SUBREG.
        (and64_operand): Do not limit CONST_INT to mask64_operand.
        (and64_2_operand): Do not limit CONST_INT to mask64_1or2_operand.
        (and_operand): Do not limit CONST_INT to mask_operand.

From-SVN: r97872

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3f99ac1b2030e08cfe12fea9545ba373c1b861e8..269275c3ee5cbb025660ed11083f41b77978394c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2005-04-08  David Edelsohn  <edelsohn@gnu.org>
+
+       PR target/20814
+       * config/rs6000/predicates.md (altivec_register_operand): Accept
+       SUBREG. 
+       (and64_operand): Do not limit CONST_INT to mask64_operand.
+       (and64_2_operand): Do not limit CONST_INT to mask64_1or2_operand.
+       (and_operand): Do not limit CONST_INT to mask_operand.
+
 2005-04-09  Hans-Peter Nilsson  <hp@axis.com>
 
        PR rtl-optimization/20466

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b8757a1fe6aedae634f66a8ee1bfcac30b073f84..e29297a0faf405d3b0c2b592a6f3a72ea68b5336 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -34,9 +34,11 @@
   
 ;; Return 1 if op is an Altivec register.
 (define_predicate "altivec_register_operand"
-  (and (match_code "reg")
-       (match_test "ALTIVEC_REGNO_P (REGNO (op))
-                   || REGNO (op) > LAST_VIRTUAL_REGISTER")))
+  (and (match_code "reg,subreg")
+       (and (match_operand 0 "register_operand")
+           (match_test "GET_CODE (op) != REG
+                        || ALTIVEC_REGNO_P (REGNO (op))
+                        || REGNO (op) > LAST_VIRTUAL_REGISTER"))))
 
 ;; Return 1 if op is XER register.
 (define_predicate "xer_operand"
@@ -531,29 +533,27 @@
 ;; Return 1 if the operand is either a non-special register or a constant
 ;; that can be used as the operand of a PowerPC64 logical AND insn.
 (define_predicate "and64_operand"
-  (if_then_else (match_code "const_int")
-    (match_operand 0 "mask64_operand")
-    (if_then_else (match_test "fixed_regs[CR0_REGNO]")
-      (match_operand 0 "gpc_reg_operand")
-      (match_operand 0 "logical_operand"))))
+  (ior (match_operand 0 "mask64_operand")
+       (if_then_else (match_test "fixed_regs[CR0_REGNO]")
+        (match_operand 0 "gpc_reg_operand")
+        (match_operand 0 "logical_operand"))))
 
 ;; Like and64_operand, but also match constants that can be implemented
 ;; with two rldicl or rldicr insns.
 (define_predicate "and64_2_operand"
-  (if_then_else (match_code "const_int")
-    (match_test "mask64_1or2_operand (op, mode, true)")
-    (if_then_else (match_test "fixed_regs[CR0_REGNO]")
-      (match_operand 0 "gpc_reg_operand")
-      (match_operand 0 "logical_operand"))))
+  (ior (and (match_code "const_int")
+           (match_test "mask64_1or2_operand (op, mode, true)"))
+       (if_then_else (match_test "fixed_regs[CR0_REGNO]")
+        (match_operand 0 "gpc_reg_operand")
+        (match_operand 0 "logical_operand"))))
 
 ;; Return 1 if the operand is either a non-special register or a
 ;; constant that can be used as the operand of a logical AND.
 (define_predicate "and_operand"
-  (if_then_else (match_code "const_int")
-    (match_operand 0 "mask_operand")
-    (if_then_else (match_test "fixed_regs[CR0_REGNO]")
-      (match_operand 0 "gpc_reg_operand")
-      (match_operand 0 "logical_operand"))))
+  (ior (match_operand 0 "mask_operand")
+       (if_then_else (match_test "fixed_regs[CR0_REGNO]")
+        (match_operand 0 "gpc_reg_operand")
+        (match_operand 0 "logical_operand"))))
 
 ;; Return 1 if the operand is a general non-special register or memory operand.
 (define_predicate "reg_or_mem_operand"