]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/msm/dpu: Adjust writeback phys encoder setup for CWB
authorJessica Zhang <quic_jesszhan@quicinc.com>
Sat, 15 Feb 2025 00:14:33 +0000 (16:14 -0800)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Wed, 5 Mar 2025 02:34:12 +0000 (04:34 +0200)
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/637490/
Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-10-a44c293cf422@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

index 648e6b3aab84957ca0401cbbc25889f0bd64b71a..849fea580a4ca55fc4a742c6b6dee7dfcdd788e4 100644 (file)
@@ -68,7 +68,7 @@ static void dpu_encoder_phys_wb_set_ot_limit(
        ot_params.num = hw_wb->idx - WB_0;
        ot_params.width = phys_enc->cached_mode.hdisplay;
        ot_params.height = phys_enc->cached_mode.vdisplay;
-       ot_params.is_wfd = true;
+       ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc);
        ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
        ot_params.vbif_idx = hw_wb->caps->vbif_idx;
        ot_params.rd = false;
@@ -111,7 +111,7 @@ static void dpu_encoder_phys_wb_set_qos_remap(
        qos_params.vbif_idx = hw_wb->caps->vbif_idx;
        qos_params.xin_id = hw_wb->caps->xin_id;
        qos_params.num = hw_wb->idx - WB_0;
-       qos_params.is_rt = false;
+       qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc);
 
        DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
                        qos_params.num,
@@ -174,6 +174,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
        struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
        struct dpu_hw_wb *hw_wb;
        struct dpu_hw_wb_cfg *wb_cfg;
+       u32 cdp_usage;
 
        if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
                DPU_ERROR("invalid encoder\n");
@@ -182,6 +183,10 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
 
        hw_wb = phys_enc->hw_wb;
        wb_cfg = &wb_enc->wb_cfg;
+       if (dpu_encoder_helper_get_cwb_mask(phys_enc))
+               cdp_usage = DPU_PERF_CDP_USAGE_RT;
+       else
+               cdp_usage = DPU_PERF_CDP_USAGE_NRT;
 
        wb_cfg->intf_mode = phys_enc->intf_mode;
        wb_cfg->roi.x1 = 0;
@@ -199,7 +204,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
                const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
 
                hw_wb->ops.setup_cdp(hw_wb, format,
-                                    perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
+                                    perf->cdp_cfg[cdp_usage].wr_enable);
        }
 
        if (hw_wb->ops.setup_outaddress)