4.9-stable patches

added patches:
	acpi-lpss-add-missing-prv_offset-setting-for-byt-cht-pwm-devices.patch

diff --git a/queue-4.9/acpi-lpss-add-missing-prv_offset-setting-for-byt-cht-pwm-devices.patch b/queue-4.9/acpi-lpss-add-missing-prv_offset-setting-for-byt-cht-pwm-devices.patch
new file mode 100644 (file)
index 0000000..d4df784
--- /dev/null
+++ b/queue-4.9/acpi-lpss-add-missing-prv_offset-setting-for-byt-cht-pwm-devices.patch
@@ -0,0 +1,50 @@
+From fdcb613d49321b5bf5d5a1bd0fba8e7c241dcc70 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Thu, 26 Apr 2018 14:10:24 +0200
+Subject: ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+commit fdcb613d49321b5bf5d5a1bd0fba8e7c241dcc70 upstream.
+
+The LPSS PWM device on on Bay Trail and Cherry Trail devices has a set
+of private registers at offset 0x800, the current lpss_device_desc for
+them already sets the LPSS_SAVE_CTX flag to have these saved/restored
+over device-suspend, but the current lpss_device_desc was not setting
+the prv_offset field, leading to the regular device registers getting
+saved/restored instead.
+
+This is causing the PWM controller to no longer work, resulting in a black
+screen,  after a suspend/resume on systems where the firmware clears the
+APB clock and reset bits at offset 0x804.
+
+This commit fixes this by properly setting prv_offset to 0x800 for
+the PWM devices.
+
+Cc: stable@vger.kernel.org
+Fixes: e1c748179754 ("ACPI / LPSS: Add Intel BayTrail ACPI mode PWM")
+Fixes: 1bfbd8eb8a7f ("ACPI / LPSS: Add ACPI IDs for Intel Braswell")
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Acked-by: Rafael J . Wysocki <rjw@rjwysocki.net>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/acpi/acpi_lpss.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/acpi/acpi_lpss.c
++++ b/drivers/acpi/acpi_lpss.c
+@@ -187,10 +187,12 @@ static const struct lpss_device_desc lpt
+ 
+ static const struct lpss_device_desc byt_pwm_dev_desc = {
+       .flags = LPSS_SAVE_CTX,
++      .prv_offset = 0x800,
+ };
+ 
+ static const struct lpss_device_desc bsw_pwm_dev_desc = {
+       .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
++      .prv_offset = 0x800,
+ };
+ 
+ static const struct lpss_device_desc byt_uart_dev_desc = {

diff --git a/queue-4.9/series b/queue-4.9/series
index e3fec43ebfbdbbdbed2604f24515f8c2d9df9ed3..271ec812dc52a35ec77dcd37bdfb3bc40f1b21b3 100644 (file)
--- a/queue-4.9/series
+++ b/queue-4.9/series
@@ -5,3 +5,4 @@ parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch
 kasan-add-no_sanitize-attribute-for-clang-builds.patch
 mark-hi-and-tasklet-softirq-synchronous.patch
 xen-netfront-don-t-cache-skb_shinfo.patch
+acpi-lpss-add-missing-prv_offset-setting-for-byt-cht-pwm-devices.patch