/* IP reg dump */
uint32_t *ip_dump_core;
- uint32_t *ip_dump_cp_queues;
+ uint32_t *ip_dump_compute_queues;
uint32_t *ip_dump_gfx_queues;
};
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
- adev->gfx.ip_dump_cp_queues = NULL;
+ adev->gfx.ip_dump_compute_queues = NULL;
} else {
- adev->gfx.ip_dump_cp_queues = ptr;
+ adev->gfx.ip_dump_compute_queues = ptr;
}
/* Allocate memory for gfx queue registers for all the instances */
gfx_v10_0_free_microcode(adev);
kfree(adev->gfx.ip_dump_core);
- kfree(adev->gfx.ip_dump_cp_queues);
+ kfree(adev->gfx.ip_dump_compute_queues);
kfree(adev->gfx.ip_dump_gfx_queues);
return 0;
adev->gfx.ip_dump_core[i]);
/* print compute queue registers for all instances */
- if (!adev->gfx.ip_dump_cp_queues)
+ if (!adev->gfx.ip_dump_compute_queues)
return;
reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
for (reg = 0; reg < reg_count; reg++) {
drm_printf(p, "%-50s \t 0x%08x\n",
gc_cp_reg_list_10[reg].reg_name,
- adev->gfx.ip_dump_cp_queues[index + reg]);
+ adev->gfx.ip_dump_compute_queues[index + reg]);
}
index += reg_count;
}
amdgpu_gfx_off_ctrl(adev, true);
/* dump compute queue registers for all instances */
- if (!adev->gfx.ip_dump_cp_queues)
+ if (!adev->gfx.ip_dump_compute_queues)
return;
reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
nv_grbm_select(adev, 1 + i, j, k, 0);
for (reg = 0; reg < reg_count; reg++) {
- adev->gfx.ip_dump_cp_queues[index + reg] =
+ adev->gfx.ip_dump_compute_queues[index + reg] =
RREG32(SOC15_REG_ENTRY_OFFSET(
gc_cp_reg_list_10[reg]));
}
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
- adev->gfx.ip_dump_cp_queues = NULL;
+ adev->gfx.ip_dump_compute_queues = NULL;
} else {
- adev->gfx.ip_dump_cp_queues = ptr;
+ adev->gfx.ip_dump_compute_queues = ptr;
}
/* Allocate memory for gfx queue registers for all the instances */
gfx_v11_0_free_microcode(adev);
kfree(adev->gfx.ip_dump_core);
- kfree(adev->gfx.ip_dump_cp_queues);
+ kfree(adev->gfx.ip_dump_compute_queues);
kfree(adev->gfx.ip_dump_gfx_queues);
return 0;
adev->gfx.ip_dump_core[i]);
/* print compute queue registers for all instances */
- if (!adev->gfx.ip_dump_cp_queues)
+ if (!adev->gfx.ip_dump_compute_queues)
return;
reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
for (reg = 0; reg < reg_count; reg++) {
drm_printf(p, "%-50s \t 0x%08x\n",
gc_cp_reg_list_11[reg].reg_name,
- adev->gfx.ip_dump_cp_queues[index + reg]);
+ adev->gfx.ip_dump_compute_queues[index + reg]);
}
index += reg_count;
}
amdgpu_gfx_off_ctrl(adev, true);
/* dump compute queue registers for all instances */
- if (!adev->gfx.ip_dump_cp_queues)
+ if (!adev->gfx.ip_dump_compute_queues)
return;
reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
/* ME0 is for GFX so start from 1 for CP */
soc21_grbm_select(adev, 1+i, j, k, 0);
for (reg = 0; reg < reg_count; reg++) {
- adev->gfx.ip_dump_cp_queues[index + reg] =
+ adev->gfx.ip_dump_compute_queues[index + reg] =
RREG32(SOC15_REG_ENTRY_OFFSET(
gc_cp_reg_list_11[reg]));
}
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
- adev->gfx.ip_dump_cp_queues = NULL;
+ adev->gfx.ip_dump_compute_queues = NULL;
} else {
- adev->gfx.ip_dump_cp_queues = ptr;
+ adev->gfx.ip_dump_compute_queues = ptr;
}
}
gfx_v9_0_free_microcode(adev);
kfree(adev->gfx.ip_dump_core);
- kfree(adev->gfx.ip_dump_cp_queues);
+ kfree(adev->gfx.ip_dump_compute_queues);
return 0;
}
adev->gfx.ip_dump_core[i]);
/* print compute queue registers for all instances */
- if (!adev->gfx.ip_dump_cp_queues)
+ if (!adev->gfx.ip_dump_compute_queues)
return;
reg_count = ARRAY_SIZE(gc_cp_reg_list_9);
for (reg = 0; reg < reg_count; reg++) {
drm_printf(p, "%-50s \t 0x%08x\n",
gc_cp_reg_list_9[reg].reg_name,
- adev->gfx.ip_dump_cp_queues[index + reg]);
+ adev->gfx.ip_dump_compute_queues[index + reg]);
}
index += reg_count;
}
amdgpu_gfx_off_ctrl(adev, true);
/* dump compute queue registers for all instances */
- if (!adev->gfx.ip_dump_cp_queues)
+ if (!adev->gfx.ip_dump_compute_queues)
return;
reg_count = ARRAY_SIZE(gc_cp_reg_list_9);
soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
for (reg = 0; reg < reg_count; reg++) {
- adev->gfx.ip_dump_cp_queues[index + reg] =
+ adev->gfx.ip_dump_compute_queues[index + reg] =
RREG32(SOC15_REG_ENTRY_OFFSET(
gc_cp_reg_list_9[reg]));
}