/* Shift the S bits to their VS bit location in mip */
int ret = rmw_mip(env, 0, ret_value, new_value << 1,
(write_mask << 1) & vsip_writable_mask & env->hideleg);
- *ret_value &= VS_MODE_INTERRUPTS;
- /* Shift the VS bits to their S bit location in vsip */
- *ret_value >>= 1;
+
+ if (ret_value) {
+ *ret_value &= VS_MODE_INTERRUPTS;
+ /* Shift the VS bits to their S bit location in vsip */
+ *ret_value >>= 1;
+ }
return ret;
}
write_mask & env->mideleg & sip_writable_mask);
}
- *ret_value &= env->mideleg;
+ if (ret_value) {
+ *ret_value &= env->mideleg;
+ }
return ret;
}
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hvip_writable_mask);
- *ret_value &= hvip_writable_mask;
-
+ if (ret_value) {
+ *ret_value &= hvip_writable_mask;
+ }
return ret;
}
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
- *ret_value &= hip_writable_mask;
-
+ if (ret_value) {
+ *ret_value &= hip_writable_mask;
+ }
return ret;
}