PCI: dwc: ep: Write BAR_MASK before iATU registers in pci_epc_set_bar()

The "DesignWare Cores PCI Express Controller Register Descriptions,
Version 4.60a", section "1.21.70 IATU_LWR_TARGET_ADDR_OFF_INBOUND_i",
fields LWR_TARGET_RW and LWR_TARGET_HW both state that:
"Field size depends on log2(BAR_MASK+1) in BAR match mode."

I.e. only the upper bits are writable, and the number of writable bits is
dependent on the configured BAR_MASK.

If we do not write the BAR_MASK before writing the iATU registers, we are
relying the reset value of the BAR_MASK being larger than the requested
BAR size (which is supplied in the struct pci_epf_bar which is passed to
pci_epc_set_bar()). The reset value of the BAR_MASK is SoC dependent.

Thus, if the struct pci_epf_bar requests a BAR size that is larger than the
reset value of the BAR_MASK, the iATU will try to write to read-only bits,
which will cause the iATU to end up redirecting to a physical address that
is different from the address that was intended.

Thus, we should always write the iATU registers after writing the BAR_MASK.

Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support")
Link: https://lore.kernel.org/r/20241213143301.4158431-9-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index f3ac7d46a855b25737465e55247b1d354a6a2133..bad588ef69a41a685b31edc831d2080be9164376 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -222,19 +222,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
        if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1))
                return -EINVAL;
 
-       reg = PCI_BASE_ADDRESS_0 + (4 * bar);
-
-       if (!(flags & PCI_BASE_ADDRESS_SPACE))
-               type = PCIE_ATU_TYPE_MEM;
-       else
-               type = PCIE_ATU_TYPE_IO;
-
-       ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar);
-       if (ret)
-               return ret;
-
        if (ep->epf_bar[bar])
-               return 0;
+               goto config_atu;
+
+       reg = PCI_BASE_ADDRESS_0 + (4 * bar);
 
        dw_pcie_dbi_ro_wr_en(pci);
 
@@ -246,9 +237,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
                dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
        }
 
-       ep->epf_bar[bar] = epf_bar;
        dw_pcie_dbi_ro_wr_dis(pci);
 
+config_atu:
+       if (!(flags & PCI_BASE_ADDRESS_SPACE))
+               type = PCIE_ATU_TYPE_MEM;
+       else
+               type = PCIE_ATU_TYPE_IO;
+
+       ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar);
+       if (ret)
+               return ret;
+
+       ep->epf_bar[bar] = epf_bar;
+
        return 0;
 }