clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()

Combine common code from rzg2l_cpg_assert() and rzg2l_cpg_deassert() into a
new __rzg2l_cpg_assert() helper to avoid code duplication. This reduces
maintenance effort and improves code clarity.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/20250903082757.115778-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index b508823f9723c27678aafb46eb28e3b04f011636..e0e1bebd98950e6ffa07f940d0ee46e263fa27e3 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1638,8 +1638,8 @@ fail:
 
 #define rcdev_to_priv(x)       container_of(x, struct rzg2l_cpg_priv, rcdev)
 
-static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
-                           unsigned long id)
+static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
+                             unsigned long id, bool assert)
 {
        struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
        const struct rzg2l_cpg_info *info = priv->info;
@@ -1647,9 +1647,13 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
        u32 mask = BIT(info->resets[id].bit);
        s8 monbit = info->resets[id].monbit;
        u32 value = mask << 16;
+       int ret;
 
-       dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
+       dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
+               assert ? "assert" : "deassert", id, CLK_RST_R(reg));
 
+       if (!assert)
+               value |= mask;
        writel(value, priv->base + CLK_RST_R(reg));
 
        if (info->has_clk_mon_regs) {
@@ -1664,37 +1668,19 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
        }
 
        return readl_poll_timeout_atomic(priv->base + reg, value,
-                                        value & mask, 10, 200);
+                                        assert == !!(value & mask), 10, 200);
+}
+
+static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
+                           unsigned long id)
+{
+       return __rzg2l_cpg_assert(rcdev, id, true);
 }
 
 static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
                              unsigned long id)
 {
-       struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
-       const struct rzg2l_cpg_info *info = priv->info;
-       unsigned int reg = info->resets[id].off;
-       u32 mask = BIT(info->resets[id].bit);
-       s8 monbit = info->resets[id].monbit;
-       u32 value = (mask << 16) | mask;
-
-       dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
-               CLK_RST_R(reg));
-
-       writel(value, priv->base + CLK_RST_R(reg));
-
-       if (info->has_clk_mon_regs) {
-               reg = CLK_MRST_R(reg);
-       } else if (monbit >= 0) {
-               reg = CPG_RST_MON;
-               mask = BIT(monbit);
-       } else {
-               /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
-               udelay(35);
-               return 0;
-       }
-
-       return readl_poll_timeout_atomic(priv->base + reg, value,
-                                        !(value & mask), 10, 200);
+       return __rzg2l_cpg_assert(rcdev, id, false);
 }
 
 static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,