* common.opt (-G): Don't define option here.
* config/g.opt: New.
* config.gcc: Use g.opt for alpha, frv, ia64, lm32, m32r, mips,
rs6000/powerpc and score targets.
* opts.c (common_handle_option): Don't handle -G here.
* config/alpha/alpha.c (alpha_handle_option): Handle -G.
* config/frv/frv.c (frv_handle_option): Handle -G.
* config/ia64/ia64.c (ia64_handle_option): Handle -G.
* config/lm32/lm32.c (lm32_handle_option, TARGET_HANDLE_OPTION):
New.
* config/m32r/m32r.c (m32r_handle_option): Handle -G.
* config/mips/mips.c (mips_handle_option): Handle -G.
* config/rs6000/rs6000.c (rs6000_handle_option) Handle -G.
* config/score/score.c (score_handle_option): Handle -G.
From-SVN: r162721
+2010-07-30 Joseph Myers <joseph@codesourcery.com>
+
+ * common.opt (-G): Don't define option here.
+ * config/g.opt: New.
+ * config.gcc: Use g.opt for alpha, frv, ia64, lm32, m32r, mips,
+ rs6000/powerpc and score targets.
+ * opts.c (common_handle_option): Don't handle -G here.
+ * config/alpha/alpha.c (alpha_handle_option): Handle -G.
+ * config/frv/frv.c (frv_handle_option): Handle -G.
+ * config/ia64/ia64.c (ia64_handle_option): Handle -G.
+ * config/lm32/lm32.c (lm32_handle_option, TARGET_HANDLE_OPTION):
+ New.
+ * config/m32r/m32r.c (m32r_handle_option): Handle -G.
+ * config/mips/mips.c (mips_handle_option): Handle -G.
+ * config/rs6000/rs6000.c (rs6000_handle_option) Handle -G.
+ * config/score/score.c (score_handle_option): Handle -G.
+
2010-07-30 Anatoly Sokolov <aesok@post.ru>
* config/mmix/mmix.c: Include basic-block.h.
-version
Common
-G
-Common Joined Separate UInteger
--G<number> Put global and static data smaller than <number> bytes into a special section (on some targets)
-
O
Common JoinedOrMissing Optimization
-O<number> Set optimization level to <number>
alpha*-*-*)
cpu_type=alpha
need_64bit_hwint=yes
+ extra_options="${extra_options} g.opt"
;;
am33_2.0-*-linux*)
cpu_type=mn10300
cpu_type=cris
;;
frv*) cpu_type=frv
+ extra_options="${extra_options} g.opt"
;;
moxie*) cpu_type=moxie
;;
ia64-*-*)
extra_headers=ia64intrin.h
need_64bit_hwint=yes
+ extra_options="${extra_options} g.opt"
;;
hppa*-*-*)
cpu_type=pa
;;
+lm32*)
+ extra_options="${extra_options} g.opt"
+ ;;
m32r*-*-*)
cpu_type=m32r
+ extra_options="${extra_options} g.opt"
;;
m68k-*-*)
extra_headers=math-68881.h
cpu_type=mips
need_64bit_hwint=yes
extra_headers="loongson.h"
+ extra_options="${extra_options} g.opt"
;;
picochip-*-*)
cpu_type=picochip
cpu_is_64bit=yes
;;
esac
+ extra_options="${extra_options} g.opt"
;;
rs6000*-*-*)
need_64bit_hwint=yes
+ extra_options="${extra_options} g.opt"
;;
score*-*-*)
cpu_type=score
+ extra_options="${extra_options} g.opt"
;;
sparc*-*-*)
cpu_type=sparc
{
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ break;
+
case OPT_mfp_regs:
if (value == 0)
target_flags |= MASK_SOFT_FP;
/* Implement TARGET_HANDLE_OPTION. */
static bool
-frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+frv_handle_option (size_t code, const char *arg, int value)
{
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ return true;
+
case OPT_mcpu_:
if (strcmp (arg, "simple") == 0)
frv_cpu_type = FRV_CPU_SIMPLE;
--- /dev/null
+; -G option (small data, some targets only).
+
+; Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+; Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+; <http://www.gnu.org/licenses/>.
+
+; See the GCC internals manual (options.texi) for a description of this file's format.
+
+; Please try to keep this file in ASCII collating order.
+
+G
+Target Joined Separate UInteger
+-G<number> Put global and static data smaller than <number> bytes into a special section (on some targets)
+
+; This comment is to ensure we retain the blank line above.
{
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ return true;
+
case OPT_mfixed_range_:
fix_range (arg);
return true;
/* Subroutines used for code generation on the Lattice Mico32 architecture.
Contributed by Jon Beniston <jon@beniston.com>
- Copyright (C) 2009 Free Software Foundation, Inc.
+ Copyright (C) 2009, 2010 Free Software Foundation, Inc.
This file is part of GCC.
static bool
lm32_legitimate_address_p (enum machine_mode mode, rtx x, bool strict);
static HOST_WIDE_INT lm32_compute_frame_size (int size);
+static bool lm32_handle_option (size_t code, const char *arg, int value);
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION lm32_handle_option
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_bool_0
#undef TARGET_RTX_COSTS
}
}
+/* Implement TARGET_HANDLE_OPTION. */
+
+static bool
+lm32_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
+{
+ switch (code)
+ {
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ return true;
+
+ default:
+ return true;
+ }
+}
+
/* Override command line options. */
void
lm32_override_options (void)
/* Subroutines used for code generation on the Renesas M32R cpu.
Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
- 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
+ 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
This file is part of GCC.
{
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ return true;
+
case OPT_m32r:
target_flags &= ~(MASK_M32R2 | MASK_M32RX);
return true;
/* Implement TARGET_HANDLE_OPTION. */
static bool
-mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+mips_handle_option (size_t code, const char *arg, int value)
{
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ return true;
+
case OPT_mabi_:
if (strcmp (arg, "32") == 0)
mips_abi = ABI_32;
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ break;
+
case OPT_mno_power:
target_flags &= ~(MASK_POWER | MASK_POWER2
| MASK_MULTIPLE | MASK_STRING);
/* Output routines for Sunplus S+CORE processor
- Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by Sunnorth.
This file is part of GCC.
/* Implement TARGET_HANDLE_OPTION. */
static bool
-score_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+score_handle_option (size_t code, const char *arg, int value)
{
switch (code)
{
+ case OPT_G:
+ g_switch_value = value;
+ g_switch_set = true;
+ return true;
+
case OPT_mscore7d:
target_flags &= ~(MASK_ALL_CPU_BITS);
target_flags |= MASK_SCORE7 | MASK_SCORE7D;
exit_after_options = true;
break;
- case OPT_G:
- g_switch_value = value;
- g_switch_set = true;
- break;
-
case OPT_O:
case OPT_Os:
case OPT_Ofast: