if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
+ else if (!main_args_p
+ && ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL])
+ opts->x_target_flags &= ~MASK_AVX256_SPLIT_UNALIGNED_LOAD;
+
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
+ else if (!main_args_p
+ && ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL])
+ opts->x_target_flags &= ~MASK_AVX256_SPLIT_UNALIGNED_STORE;
/* Enable 128-bit AVX instruction generation
for the auto-vectorizer. */
--- /dev/null
+/* PR target/100093 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=znver1" } */
+/* { dg-final { scan-assembler-not "vextractf128" } } */
+
+__attribute__((target("tune=skylake-avx512")))
+void fill_avx2(double *__restrict__ data, int n, double value)
+{
+ for (int i = 0; i < n * 16; i++) {
+ data[i] = value;
+ }
+}