RISC-V: testsuite: restrict big endian test to non vector

RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/pr117595.c: Restrict to non vector targets.

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

diff --git a/gcc/testsuite/gcc.target/riscv/pr117595.c b/gcc/testsuite/gcc.target/riscv/pr117595.c
index a870df08ee4be6b19fc4a0128cdc5fce877ef322..156b9388d6e451ccaccceed45a7c3ad3e1ed15c4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/pr117595.c
+++ b/gcc/testsuite/gcc.target/riscv/pr117595.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_v } } } */
 /* { dg-options "-mbig-endian" } */
 
 _Atomic enum { E0 } e;