arm64: dts: mediatek: mt7988: Add CPU OPP table for clock scaling

Add operating points defining frequency/voltages of cpu cores.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 5e53ea47f1591fdc21e092f2b589a4394f804b58..a7954bf5c81ed10eba941b1a46a96390f1f97858 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -21,6 +21,10 @@
                        reg = <0x0>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu@1 {
@@ -28,6 +32,10 @@
                        reg = <0x1>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu@2 {
@@ -35,6 +43,10 @@
                        reg = <0x2>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu@3 {
@@ -42,6 +54,32 @@
                        reg = <0x3>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+
+               cluster0_opp: opp-table-0 {
+                       compatible = "operating-points-v2";
+                       opp-shared;
+
+                       opp-800000000 {
+                               opp-hz = /bits/ 64 <800000000>;
+                               opp-microvolt = <850000>;
+                       };
+                       opp-1100000000 {
+                               opp-hz = /bits/ 64 <1100000000>;
+                               opp-microvolt = <850000>;
+                       };
+                       opp-1500000000 {
+                               opp-hz = /bits/ 64 <1500000000>;
+                               opp-microvolt = <850000>;
+                       };
+                       opp-1800000000 {
+                               opp-hz = /bits/ 64 <1800000000>;
+                               opp-microvolt = <900000>;
+                       };
                };
        };