arm64: dts: ti: k3-am642-evm: Add overlay for PCIe0 EP mode

Add overlay to enable the PCIe0 instance of PCIe on AM642-EVM in
Endpoint mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240930103413.3085689-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index a4516374455962efeae86f4a8461c481938c207f..5982619d4a280f50f9f6dadeaacc68ce8d4150db 100644 (file)
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -47,6 +47,7 @@ k3-am642-hummingboard-t-usb3-dtbs := \
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-pcie0-ep.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb
@@ -169,6 +170,8 @@ k3-am642-evm-icssg1-dualemac-dtbs := \
        k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo
 k3-am642-evm-icssg1-dualemac-mii-dtbs := \
        k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo
+k3-am642-evm-pcie0-ep-dtbs := \
+       k3-am642-evm.dtb k3-am642-evm-pcie0-ep.dtbo
 k3-am642-phyboard-electra-disable-eth-phy-dtbs := \
        k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo
 k3-am642-phyboard-electra-disable-rtc-dtbs := \
@@ -220,6 +223,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-am62p5-sk-csi2-tevi-ov5640.dtb \
        k3-am642-evm-icssg1-dualemac.dtb \
        k3-am642-evm-icssg1-dualemac-mii.dtb \
+       k3-am642-evm-pcie0-ep.dtb \
        k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
        k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
        k3-am68-sk-base-board-csi2-dual-imx219.dtb \

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
new file mode 100644 (file)
index 0000000..6b02953
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
+ * AM642 EVM.
+ *
+ * AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+       status = "disabled";
+};
+
+&cbass_main {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&gic500>;
+
+       pcie0_ep: pcie-ep@f102000 {
+               compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
+               reg = <0x00 0x0f102000 0x00 0x1000>,
+                     <0x00 0x0f100000 0x00 0x400>,
+                     <0x00 0x0d000000 0x00 0x00800000>,
+                     <0x00 0x68000000 0x00 0x08000000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+               max-link-speed = <2>;
+               num-lanes = <1>;
+               power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 114 0>;
+               clock-names = "fck";
+               max-functions = /bits/ 8 <1>;
+               phys = <&serdes0_pcie_link>;
+               phy-names = "pcie-phy";
+               ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+       };
+};