arm64: dts: morello: Add support for fvp dts

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

Introduce Morello fvp dts.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 869667bef7c08fa144f294483c0d10de83332d95..f30ee045dc95935e541a605a7e23f71258413d50 100644 (file)
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
-dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb

diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts
new file mode 100644 (file)
index 0000000..2072c0b
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello-fvp.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+#include "morello.dtsi"
+
+/ {
+       model = "Arm Morello Fixed Virtual Platform";
+       compatible = "arm,morello-fvp", "arm,morello";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       bp_refclock24mhz: clock-24000000 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "bp:clock24mhz";
+       };
+
+       block_0: virtio_block@1c170000 {
+               compatible = "virtio,mmio";
+               reg = <0x0 0x1c170000 0x0 0x200>;
+               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       net_0: virtio_net@1c180000 {
+               compatible = "virtio,mmio";
+               reg = <0x0 0x1c180000 0x0 0x200>;
+               interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       rng_0: virtio_rng@1c190000 {
+               compatible = "virtio,mmio";
+               reg = <0x0 0x1c190000 0x0 0x200>;
+               interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       p9_0: virtio_p9@1c1a0000 {
+               compatible = "virtio,mmio";
+               reg = <0x0 0x1c1a0000 0x0 0x200>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       kmi_0: kmi@1c150000 {
+               compatible = "arm,pl050", "arm,primecell";
+               reg = <0x0 0x1c150000 0x0 0x1000>;
+               interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
+               clock-names = "KMIREFCLK", "apb_pclk";
+       };
+
+       kmi_1: kmi@1c160000 {
+               compatible = "arm,pl050", "arm,primecell";
+               reg = <0x0 0x1c160000 0x0 0x1000>;
+               interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
+               clock-names = "KMIREFCLK", "apb_pclk";
+       };
+
+       eth_0: ethernet@1d100000 {
+               compatible = "smsc,lan91c111";
+               reg = <0x0 0x1d100000 0x0 0x10000>;
+               interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+};