target-mips: fix wrong microMIPS opcode encoding

While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.

[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
    Application-Specific Extension to the microMIPS32 Architecture

Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 6801038bc52d61f81ac8a25fbe392f1bad982887)

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 4e04e97ce24243516a47e25ec7b785d58ee6ba45..49907bb6f48387a8733b3668399d7b61aa537d9f 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9486,7 +9486,7 @@ enum {
 
     /* bits 13..12 for 0x32 */
     MULT_ACC = 0x0,
-    MULTU_ACC = 0x0,
+    MULTU_ACC = 0x1,
 
     /* bits 15..12 for 0x2c */
     SEB = 0x2,