#include "dwxgmac2.h"
#include "stmmac.h"
-#define MII_BUSY 0x00000001
-#define MII_WRITE 0x00000002
-#define MII_DATA_MASK GENMASK(15, 0)
+#define MII_ADDR_GBUSY BIT(0)
+#define MII_ADDR_GWRITE BIT(1)
+#define MII_DATA_GD_MASK GENMASK(15, 0)
/* GMAC4 defines */
#define MII_GMAC4_GOC_SHIFT 2
return ((pa << mii_regs->addr_shift) & mii_regs->addr_mask) |
((gr << mii_regs->reg_shift) & mii_regs->reg_mask) |
priv->gmii_address_bus_config |
- MII_BUSY;
+ MII_ADDR_GBUSY;
}
static int stmmac_mdio_access(struct stmmac_priv *priv, unsigned int pa,
if (ret < 0)
return ret;
- ret = stmmac_mdio_wait(mii_address, MII_BUSY);
+ ret = stmmac_mdio_wait(mii_address, MII_ADDR_GBUSY);
if (ret)
goto out;
writel(data, mii_data);
writel(addr, mii_address);
- ret = stmmac_mdio_wait(mii_address, MII_BUSY);
+ ret = stmmac_mdio_wait(mii_address, MII_ADDR_GBUSY);
if (ret)
goto out;
/* Read the data from the MII data register if in read mode */
- ret = read ? readl(mii_data) & MII_DATA_MASK : 0;
+ ret = read ? readl(mii_data) & MII_DATA_GD_MASK : 0;
out:
pm_runtime_put(priv->device);
if (priv->plat->has_gmac4)
cmd = MII_GMAC4_WRITE;
else
- cmd = MII_WRITE;
+ cmd = MII_ADDR_GWRITE;
return stmmac_mdio_write(priv, phyaddr, phyreg, cmd, phydata);
}