]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
hw/pci-host/designware: Fix ATU_UPPER_TARGET register access
authorPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 31 Mar 2025 14:46:13 +0000 (16:46 +0200)
committerMichael Tokarev <mjt@tls.msk.ru>
Sat, 5 Apr 2025 13:45:45 +0000 (16:45 +0300)
Fix copy/paste error writing to the ATU_UPPER_TARGET
register, we want to update the upper 32 bits.

Cc: qemu-stable@nongnu.org
Reported-by: Joey <jeundery@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861
Fixes: d64e5eabc4c ("pci: Add support for Designware IP block")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-Id: <20250331152041.74533-2-philmd@linaro.org>
(cherry picked from commit 04e99f9eb7920b0f0fcce65686c3bedf5e32a1f9)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
hw/pci-host/designware.c

index c3fc37b90478158482f23bcaa2ac07c8a99b16d0..cc3ff0a45a5c557784bd72b177e45f784501caa8 100644 (file)
@@ -362,7 +362,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
 
     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
         viewport->target &= 0x00000000FFFFFFFFULL;
-        viewport->target |= val;
+        viewport->target |= (uint64_t)val << 32;
         break;
 
     case DESIGNWARE_PCIE_ATU_LIMIT: