drm/amd/display: Insert dccg log for easy debug

[why]
Log for sequence tracking

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 0ce9489ac6b728ba16c0c3873b59c4a40ddffcd3..de6d62401362e7dec1afe18d2216d7ab0c1af65f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -39,6 +39,7 @@
 
 #define CTX \
        dccg_dcn->base.ctx
+#include "logger_types.h"
 #define DC_LOGGER \
        dccg->ctx->logger
 
@@ -1136,7 +1137,7 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg,
        default:
                break;
        }
-       //DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable);
+       DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable);
 
 }
 
@@ -1406,6 +1407,10 @@ static void dccg35_set_dtbclk_dto(
                 * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the
                 * programming is handled in program_pix_clk() regardless, so it can be removed from here.
                 */
+               DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO enabled: pixclk_khz=%d, ref_dtbclk_khz=%d, req_dtbclk_khz=%d, phase=%d, modulo=%d\n",
+                               __func__, params->otg_inst, params->pixclk_khz,
+                               params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo);
+
        } else {
                switch (params->otg_inst) {
                case 0:
@@ -1431,6 +1436,8 @@ static void dccg35_set_dtbclk_dto(
 
                REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
                REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
+
+               DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO disabled\n", __func__, params->otg_inst);
        }
 }
 
@@ -1475,6 +1482,8 @@ static void dccg35_set_dpstreamclk(
                BREAK_TO_DEBUGGER();
                return;
        }
+       DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_EN = %d, DPSTREAMCLK_SRC_SEL = %d\n",
+                       __func__, dp_hpo_inst, (src == REFCLK) ? 0 : 1, otg_inst);
 }
 
 
@@ -1514,6 +1523,8 @@ static void dccg35_set_dpstreamclk_root_clock_gating(
                BREAK_TO_DEBUGGER();
                return;
        }
+       DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_ROOT_GATE_DISABLE = %d\n",
+                       __func__, dp_hpo_inst, enable ? 1 : 0);
 }
 
 
@@ -1553,7 +1564,7 @@ static void dccg35_set_physymclk_root_clock_gating(
                BREAK_TO_DEBUGGER();
                return;
        }
-       //DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE:\n", __func__, phy_inst, enable ? 0 : 1);
+       DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE: %d\n", __func__, phy_inst, enable ? 0 : 1);
 
 }
 
@@ -1626,6 +1637,8 @@ static void dccg35_set_physymclk(
                BREAK_TO_DEBUGGER();
                return;
        }
+       DC_LOG_DEBUG("%s: phy_inst(%d) PHYxSYMCLK_EN = %d, PHYxSYMCLK_SRC_SEL = %d\n",
+                       __func__, phy_inst, force_enable ? 1 : 0, clk_src);
 }
 
 static void dccg35_set_valid_pixel_rate(
@@ -1673,6 +1686,7 @@ static void dccg35_dpp_root_clock_control(
        }
 
        dccg->dpp_clock_gated[dpp_inst] = !clock_on;
+       DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on);
 }
 
 static void dccg35_disable_symclk32_se(
@@ -1731,6 +1745,7 @@ static void dccg35_disable_symclk32_se(
                BREAK_TO_DEBUGGER();
                return;
        }
+
 }
 
 static void dccg35_init_cb(struct dccg *dccg)
@@ -1738,7 +1753,6 @@ static void dccg35_init_cb(struct dccg *dccg)
        (void)dccg;
        /* Any RCG should be done when driver enter low power mode*/
 }
-
 void dccg35_init(struct dccg *dccg)
 {
        int otg_inst;
@@ -1753,6 +1767,8 @@ void dccg35_init(struct dccg *dccg)
                for (otg_inst = 0; otg_inst < 2; otg_inst++) {
                        dccg31_disable_symclk32_le(dccg, otg_inst);
                        dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);
+                       DC_LOG_DEBUG("%s: OTG%d SYMCLK32_LE disabled and root clock gating disabled\n",
+                                       __func__, otg_inst);
                }
 
 //     if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
@@ -1765,6 +1781,8 @@ void dccg35_init(struct dccg *dccg)
                        dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst,
                                                otg_inst);
                        dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);
+                       DC_LOG_DEBUG("%s: OTG%d DPSTREAMCLK disabled and root clock gating disabled\n",
+                                       __func__, otg_inst);
                }
 
 /*