microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al declaration

Removed unused code which provides information of various
I/O regions.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Link: https://lore.kernel.org/r/20221025065214.4663-11-thippeswamy.havalige@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index cd9ae71348a44be8e32c4b5b0ec5eeaf501d5805..9c89ae4cdc00594bcc82668e7282df0172621535 100644 (file)
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -29,17 +29,9 @@ struct pci_controller {
        struct list_head list_node;
        struct device *parent;
 
-       int first_busno;
-       int last_busno;
-
        void __iomem *io_base_virt;
        resource_size_t io_base_phys;
 
-       /* Some machines (PReP) have a non 1:1 mapping of
-        * the PCI memory space in the CPU bus space
-        */
-       resource_size_t pci_mem_offset;
-
        /* Currently, we limit ourselves to 1 IO range and 3 mem
         * ranges since the common pci_bus structure can't handle more
         */

diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index 6da7523d9613de462d86c331558e07dec999e56a..52d572dd41ba9e849c947321d70217e8bf655b70 100644 (file)
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -21,13 +21,6 @@
 #define PCIBIOS_MIN_IO         0x1000
 #define PCIBIOS_MIN_MEM                0x10000000
 
-/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
-#define IOBASE_BRIDGE_NUMBER   0
-#define IOBASE_MEMORY          1
-#define IOBASE_IO              2
-#define IOBASE_ISA_IO          3
-#define IOBASE_ISA_MEM         4
-
 /*
  * Set this to 1 if you want the kernel to re-assign all PCI
  * bus numbers (don't do that on ppc64 yet !)

diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 555281c389ff69f4a303d7585d1f0e094e8a628f..a1de8532a04e59c732ac03310d02532376185945 100644 (file)
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -38,9 +38,6 @@
 static DEFINE_SPINLOCK(hose_spinlock);
 LIST_HEAD(hose_list);
 
-/* ISA Memory physical address */
-resource_size_t isa_mem_base;
-
 unsigned long isa_io_base;
 EXPORT_SYMBOL(isa_io_base);
 
@@ -92,44 +89,3 @@ int pci_proc_domain(struct pci_bus *bus)
 {
        return pci_domain_nr(bus);
 }
-
-static struct pci_controller *pci_bus_to_hose(int bus)
-{
-       struct pci_controller *hose, *tmp;
-
-       list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
-               if (bus >= hose->first_busno && bus <= hose->last_busno)
-                       return hose;
-       return NULL;
-}
-
-/* Provide information on locations of various I/O regions in physical
- * memory.  Do this on a per-card basis so that we choose the right
- * root bridge.
- * Note that the returned IO or memory base is a physical address
- */
-
-long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
-{
-       struct pci_controller *hose;
-       long result = -EOPNOTSUPP;
-
-       hose = pci_bus_to_hose(bus);
-       if (!hose)
-               return -ENODEV;
-
-       switch (which) {
-       case IOBASE_BRIDGE_NUMBER:
-               return (long)hose->first_busno;
-       case IOBASE_MEMORY:
-               return (long)hose->pci_mem_offset;
-       case IOBASE_IO:
-               return (long)hose->io_base_phys;
-       case IOBASE_ISA_IO:
-               return (long)isa_io_base;
-       case IOBASE_ISA_MEM:
-               return (long)isa_mem_base;
-       }
-
-       return result;
-}