arm64: dts: rockchip: Add SFC nodes for rk3576

The rk3576 SoC has 2 SFC cores that provide FSPI functions.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Link: https://lore.kernel.org/r/20250228145304.581349-2-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 12aee9018b9f19b1607cb71437ff7bc3b4712128..edfa0326f2996d79e696f36befdb89c3524b98d4 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1334,6 +1334,17 @@
                        };
                };
 
+               sfc1: spi@2a300000 {
+                       compatible = "rockchip,sfc";
+                       reg = <0x0 0x2a300000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
+                       clock-names = "clk_sfc", "hclk_sfc";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                sdmmc: mmc@2a310000 {
                        compatible = "rockchip,rk3576-dw-mshc";
                        reg = <0x0 0x2a310000 0x0 0x4000>;
@@ -1373,6 +1384,17 @@
                        status = "disabled";
                };
 
+               sfc0: spi@2a340000 {
+                       compatible = "rockchip,sfc";
+                       reg = <0x0 0x2a340000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
+                       clock-names = "clk_sfc", "hclk_sfc";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                otp: otp@2a580000 {
                        compatible = "rockchip,rk3576-otp";
                        reg = <0x0 0x2a580000 0x0 0x400>;