]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
clk: qcom: x1e80100-dispcc: Add USB4 router link resets
authorKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tue, 18 Nov 2025 17:33:12 +0000 (18:33 +0100)
committerBjorn Andersson <andersson@kernel.org>
Tue, 18 Nov 2025 22:11:37 +0000 (16:11 -0600)
The router link clock branches also feature some reset logic, which is
required to properly power sequence the hardware for DP tunneling over
USB4.

Describe these missing resets.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-topic-usb4_x1e_dispcc-v1-2-14c68d842c71@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/dispcc-x1e80100.c

index 40069eba41f241f06b061774c051374896685633..aa7fd43969f9c8f762e0b96e764572dc34863054 100644 (file)
@@ -1618,6 +1618,9 @@ static struct clk_regmap *disp_cc_x1e80100_clocks[] = {
 
 static const struct qcom_reset_map disp_cc_x1e80100_resets[] = {
        [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
+       [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8044, .bit = 2 },
+       [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8068, .bit = 2 },
+       [DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8088, .bit = 2 },
        [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
        [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
 };