target/119010 - add missing DF load/store reservations for znver4 and znver5

The following resolves missing reservations for DFmode *movdf_internal
loads and stores, visible as 'nothing' in -fsched-verbose=2 dumps.

	PR target/119010
	* config/i386/zn4zn5.md (znver4_sse_mov_fp, znver4_sse_mov_fp_load,
	znver5_sse_mov_fp_load, znver4_sse_mov_fp_store,
	znver5_sse_mov_fp_store): Also match V1SF and DF.

diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md
index bc7712db6288d03b0228a6f2ee34c0be852540b2..954cdc528d6601a3edb91c708b5920e79290762d 100644 (file)
--- a/gcc/config/i386/zn4zn5.md
+++ b/gcc/config/i386/zn4zn5.md
@@ -1012,35 +1012,35 @@
 (define_insn_reservation "znver4_sse_mov_fp" 1
                         (and (eq_attr "cpu" "znver4,znver5")
                              (and (eq_attr "type" "ssemov")
-                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
+                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF")
                                    (eq_attr "memory" "none"))))
                         "znver4-direct,znver4-fpu")
 
 (define_insn_reservation "znver4_sse_mov_fp_load" 6
                         (and (eq_attr "cpu" "znver4")
                              (and (eq_attr "type" "ssemov")
-                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
+                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF")
                                    (eq_attr "memory" "load"))))
                         "znver4-direct,znver4-load,znver4-fpu")
 
 (define_insn_reservation "znver5_sse_mov_fp_load" 6
                         (and (eq_attr "cpu" "znver5")
                              (and (eq_attr "type" "ssemov")
-                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
+                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF")
                                    (eq_attr "memory" "load"))))
                         "znver4-direct,znver5-load,znver4-fpu")
 
 (define_insn_reservation "znver4_sse_mov_fp_store" 1
                         (and (eq_attr "cpu" "znver4")
                              (and (eq_attr "type" "ssemov")
-                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
+                                  (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF")
                                    (eq_attr "memory" "store"))))
                         "znver4-direct,znver4-fp-store")
 
 (define_insn_reservation "znver5_sse_mov_fp_store" 1
                         (and (eq_attr "cpu" "znver5")
                              (and (eq_attr "type" "ssemov")
-                                  (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
+                                  (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF")
                                    (eq_attr "memory" "store"))))
                         "znver4-direct,znver5-fp-store256")