3.10-stable patches

added patches:
	bus-mvebu-pass-the-coherency-availability-information-at-init-time.patch

diff --git a/queue-3.10/bus-mvebu-pass-the-coherency-availability-information-at-init-time.patch b/queue-3.10/bus-mvebu-pass-the-coherency-availability-information-at-init-time.patch
new file mode 100644 (file)
index 0000000..891f09f
--- /dev/null
+++ b/queue-3.10/bus-mvebu-pass-the-coherency-availability-information-at-init-time.patch
@@ -0,0 +1,188 @@
+From 5686a1e5aa436c49187a60052d5885fb1f541ce6 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Mon, 14 Apr 2014 15:47:01 +0200
+Subject: bus: mvebu: pass the coherency availability information at init time
+
+From: Greg Ungerer <gerg@uclinux.org>
+
+commit 5686a1e5aa436c49187a60052d5885fb1f541ce6 upstream.
+
+Until now, the mvebu-mbus was guessing by itself whether hardware I/O
+coherency was available or not by poking into the Device Tree to see
+if the coherency fabric Device Tree node was present or not.
+
+However, on some upcoming SoCs, the presence or absence of the
+coherency fabric DT node isn't sufficient: in CONFIG_SMP, the
+coherency can be enabled, but not in !CONFIG_SMP.
+
+In order to clean this up, the mvebu_mbus_dt_init() function is
+extended to get a boolean argument telling whether coherency is
+enabled or not. Therefore, the logic to decide whether coherency is
+available or not now belongs to the core SoC code instead of the
+mvebu-mbus driver itself, which is much better.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Link: https://lkml.kernel.org/r/1397483228-25625-4-git-send-email-thomas.petazzoni@free-electrons.com
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+
+[ Greg Ungerer: back ported to linux-3.10.y
+  Back port necessary due to large code differences in affected files.
+  This change in combination with commit e553554536 ("ARM: mvebu: disable
+  I/O coherency on non-SMP situations on Armada 370/375/38x/XP") is
+  critical to the hardware I/O coherency being set correctly by both the
+  mbus driver and all peripheral hardware drivers. Without this change
+  drivers will incorrectly enable I/O coherency window attributes and
+  this causes rare unreliable system behavior including oops. ]
+
+Signed-off-by: Greg Ungerer <gerg@uclinux.org>
+Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+v2:
+* rebase on top of 3.10.82
+* include all of original commit mesage
+
+ arch/arm/mach-dove/common.c         |    2 +-
+ arch/arm/mach-kirkwood/common.c     |    2 +-
+ arch/arm/mach-mv78xx0/common.c      |    4 ++--
+ arch/arm/mach-mvebu/armada-370-xp.c |    3 ++-
+ arch/arm/mach-mvebu/coherency.c     |   15 +++++++++++++++
+ arch/arm/mach-mvebu/coherency.h     |    1 +
+ arch/arm/mach-orion5x/common.c      |    2 +-
+ drivers/bus/mvebu-mbus.c            |    5 ++---
+ include/linux/mbus.h                |    2 +-
+ 9 files changed, 26 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/mach-dove/common.c
++++ b/arch/arm/mach-dove/common.c
+@@ -226,7 +226,7 @@ void __init dove_init_early(void)
+       orion_time_set_base(TIMER_VIRT_BASE);
+       mvebu_mbus_init("marvell,dove-mbus",
+                       BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
+-                      DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
++                      DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ, 0);
+ }
+ 
+ static int __init dove_find_tclk(void)
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -530,7 +530,7 @@ void __init kirkwood_init_early(void)
+ 
+       mvebu_mbus_init("marvell,kirkwood-mbus",
+                       BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
+-                      DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
++                      DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ, 0);
+ }
+ 
+ int kirkwood_tclk;
+--- a/arch/arm/mach-mv78xx0/common.c
++++ b/arch/arm/mach-mv78xx0/common.c
+@@ -337,11 +337,11 @@ void __init mv78xx0_init_early(void)
+       if (mv78xx0_core_index() == 0)
+               mvebu_mbus_init("marvell,mv78xx0-mbus",
+                               BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
+-                              DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
++                              DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ, 0);
+       else
+               mvebu_mbus_init("marvell,mv78xx0-mbus",
+                               BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
+-                              DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
++                              DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ, 0);
+ }
+ 
+ void __init_refok mv78xx0_timer_init(void)
+--- a/arch/arm/mach-mvebu/armada-370-xp.c
++++ b/arch/arm/mach-mvebu/armada-370-xp.c
+@@ -66,7 +66,8 @@ void __init armada_370_xp_init_early(voi
+                       ARMADA_370_XP_MBUS_WINS_BASE,
+                       ARMADA_370_XP_MBUS_WINS_SIZE,
+                       ARMADA_370_XP_SDRAM_WINS_BASE,
+-                      ARMADA_370_XP_SDRAM_WINS_SIZE);
++                      ARMADA_370_XP_SDRAM_WINS_SIZE,
++                      coherency_available());
+ 
+ #ifdef CONFIG_CACHE_L2X0
+       l2x0_of_init(0, ~0UL);
+--- a/arch/arm/mach-mvebu/coherency.c
++++ b/arch/arm/mach-mvebu/coherency.c
+@@ -137,6 +137,20 @@ static struct notifier_block mvebu_hwcc_
+       .notifier_call = mvebu_hwcc_platform_notifier,
+ };
+ 
++/*
++ * Keep track of whether we have IO hardware coherency enabled or not.
++ * On Armada 370's we will not be using it for example. We need to make
++ * that available [through coherency_available()] so the mbus controller
++ * doesn't enable the IO coherency bit in the attribute bits of the
++ * chip selects.
++ */
++static int coherency_enabled;
++
++int coherency_available(void)
++{
++      return coherency_enabled;
++}
++
+ int __init coherency_init(void)
+ {
+       struct device_node *np;
+@@ -170,6 +184,7 @@ int __init coherency_init(void)
+               coherency_base = of_iomap(np, 0);
+               coherency_cpu_base = of_iomap(np, 1);
+               set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
++              coherency_enabled = 1;
+               bus_register_notifier(&platform_bus_type,
+                                       &mvebu_hwcc_platform_nb);
+       }
+--- a/arch/arm/mach-mvebu/coherency.h
++++ b/arch/arm/mach-mvebu/coherency.h
+@@ -19,6 +19,7 @@ int coherency_get_cpu_count(void);
+ #endif
+ 
+ int set_cpu_coherent(int cpu_id, int smp_group_id);
++int coherency_available(void);
+ int coherency_init(void);
+ 
+ #endif        /* __MACH_370_XP_COHERENCY_H */
+--- a/arch/arm/mach-orion5x/common.c
++++ b/arch/arm/mach-orion5x/common.c
+@@ -213,7 +213,7 @@ void __init orion5x_init_early(void)
+               mbus_soc_name = NULL;
+       mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
+                       ORION5X_BRIDGE_WINS_SZ,
+-                      ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
++                      ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ, 0);
+ }
+ 
+ void orion5x_setup_wins(void)
+--- a/drivers/bus/mvebu-mbus.c
++++ b/drivers/bus/mvebu-mbus.c
+@@ -838,7 +838,7 @@ fs_initcall(mvebu_mbus_debugfs_init);
+ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
+                          size_t mbuswins_size,
+                          phys_addr_t sdramwins_phys_base,
+-                         size_t sdramwins_size)
++                         size_t sdramwins_size, int is_coherent)
+ {
+       struct mvebu_mbus_state *mbus = &mbus_state;
+       const struct of_device_id *of_id;
+@@ -865,8 +865,7 @@ int __init mvebu_mbus_init(const char *s
+               return -ENOMEM;
+       }
+ 
+-      if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
+-              mbus->hw_io_coherency = 1;
++      mbus->hw_io_coherency = is_coherent;
+ 
+       for (win = 0; win < mbus->soc->num_wins; win++)
+               mvebu_mbus_disable_window(mbus, win);
+--- a/include/linux/mbus.h
++++ b/include/linux/mbus.h
+@@ -67,6 +67,6 @@ int mvebu_mbus_add_window(const char *de
+ int mvebu_mbus_del_window(phys_addr_t base, size_t size);
+ int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
+                   size_t mbus_size, phys_addr_t sdram_phys_base,
+-                  size_t sdram_size);
++                  size_t sdram_size, int is_coherent);
+ 
+ #endif /* __LINUX_MBUS_H */

diff --git a/queue-3.10/series b/queue-3.10/series
index 444999480127a724942cfdaae42ca57fa0ecf2a1..a1d141c070b15dd8565cd87ca110d044c09d79ce 100644 (file)
--- a/queue-3.10/series
+++ b/queue-3.10/series
@@ -19,3 +19,4 @@ ipv6-update-ip6_rt_last_gc-every-time-gc-is-run.patch
 d_walk-might-skip-too-much.patch
 arm-clk-imx6q-refine-sata-s-parent.patch
 kvm-nsvm-check-for-nrips-support-before-updating-control-field.patch
+bus-mvebu-pass-the-coherency-availability-information-at-init-time.patch