5.15-stable patches

added patches:
	can-m_can-make-custom-bittiming-fields-const.patch
	can-m_can-pci-use-custom-bit-timings-for-elkhart-lake.patch
	revert-can-m_can-remove-support-for-custom-bit-timing.patch

diff --git a/queue-5.15/can-m_can-make-custom-bittiming-fields-const.patch b/queue-5.15/can-m_can-make-custom-bittiming-fields-const.patch
new file mode 100644 (file)
index 0000000..cc6fb32
--- /dev/null
+++ b/queue-5.15/can-m_can-make-custom-bittiming-fields-const.patch
@@ -0,0 +1,33 @@
+From ea22ba40debee29ee7257c42002409899e9311c1 Mon Sep 17 00:00:00 2001
+From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+Date: Mon, 15 Nov 2021 10:18:51 +0100
+Subject: can: m_can: make custom bittiming fields const
+
+From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+
+commit ea22ba40debee29ee7257c42002409899e9311c1 upstream.
+
+The assigned timing structs will be defined a const anyway, so we can
+avoid a few casts by declaring the struct fields as const as well.
+
+Link: https://lore.kernel.org/all/4508fa4e639164b2584c49a065d90c78a91fa568.1636967198.git.matthias.schiffer@ew.tq-group.com
+Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/can/m_can/m_can.h |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/can/m_can/m_can.h
++++ b/drivers/net/can/m_can/m_can.h
+@@ -85,8 +85,8 @@ struct m_can_classdev {
+       struct sk_buff *tx_skb;
+       struct phy *transceiver;
+ 
+-      struct can_bittiming_const *bit_timing;
+-      struct can_bittiming_const *data_timing;
++      const struct can_bittiming_const *bit_timing;
++      const struct can_bittiming_const *data_timing;
+ 
+       struct m_can_ops *ops;
+ 

diff --git a/queue-5.15/can-m_can-pci-use-custom-bit-timings-for-elkhart-lake.patch b/queue-5.15/can-m_can-pci-use-custom-bit-timings-for-elkhart-lake.patch
new file mode 100644 (file)
index 0000000..90d2406
--- /dev/null
+++ b/queue-5.15/can-m_can-pci-use-custom-bit-timings-for-elkhart-lake.patch
@@ -0,0 +1,119 @@
+From ea4c1787685dbf9842046f05b6390b6901ee6ba2 Mon Sep 17 00:00:00 2001
+From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+Date: Mon, 15 Nov 2021 10:18:52 +0100
+Subject: can: m_can: pci: use custom bit timings for Elkhart Lake
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+
+commit ea4c1787685dbf9842046f05b6390b6901ee6ba2 upstream.
+
+The relevant datasheet [1] specifies nonstandard limits for the bit timing
+parameters. While it is unclear what the exact effect of violating these
+limits is, it seems like a good idea to adhere to the documentation.
+
+[1] Intel Atom® x6000E Series, and Intel® Pentium® and Celeron® N and J
+    Series Processors for IoT Applications Datasheet,
+    Volume 2 (Book 3 of 3), July 2021, Revision 001
+
+Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel Elkhart Lake")
+Link: https://lore.kernel.org/all/9eba5d7c05a48ead4024ffa6e5926f191d8c6b38.1636967198.git.matthias.schiffer@ew.tq-group.com
+Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/can/m_can/m_can_pci.c |   48 ++++++++++++++++++++++++++++++++++----
+ 1 file changed, 44 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/can/m_can/m_can_pci.c
++++ b/drivers/net/can/m_can/m_can_pci.c
+@@ -18,9 +18,14 @@
+ 
+ #define M_CAN_PCI_MMIO_BAR            0
+ 
+-#define M_CAN_CLOCK_FREQ_EHL          200000000
+ #define CTL_CSR_INT_CTL_OFFSET                0x508
+ 
++struct m_can_pci_config {
++      const struct can_bittiming_const *bit_timing;
++      const struct can_bittiming_const *data_timing;
++      unsigned int clock_freq;
++};
++
+ struct m_can_pci_priv {
+       struct m_can_classdev cdev;
+ 
+@@ -84,9 +89,40 @@ static struct m_can_ops m_can_pci_ops =
+       .read_fifo = iomap_read_fifo,
+ };
+ 
++static const struct can_bittiming_const m_can_bittiming_const_ehl = {
++      .name = KBUILD_MODNAME,
++      .tseg1_min = 2,         /* Time segment 1 = prop_seg + phase_seg1 */
++      .tseg1_max = 64,
++      .tseg2_min = 1,         /* Time segment 2 = phase_seg2 */
++      .tseg2_max = 128,
++      .sjw_max = 128,
++      .brp_min = 1,
++      .brp_max = 512,
++      .brp_inc = 1,
++};
++
++static const struct can_bittiming_const m_can_data_bittiming_const_ehl = {
++      .name = KBUILD_MODNAME,
++      .tseg1_min = 2,         /* Time segment 1 = prop_seg + phase_seg1 */
++      .tseg1_max = 16,
++      .tseg2_min = 1,         /* Time segment 2 = phase_seg2 */
++      .tseg2_max = 8,
++      .sjw_max = 4,
++      .brp_min = 1,
++      .brp_max = 32,
++      .brp_inc = 1,
++};
++
++static const struct m_can_pci_config m_can_pci_ehl = {
++      .bit_timing = &m_can_bittiming_const_ehl,
++      .data_timing = &m_can_data_bittiming_const_ehl,
++      .clock_freq = 200000000,
++};
++
+ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
+ {
+       struct device *dev = &pci->dev;
++      const struct m_can_pci_config *cfg;
+       struct m_can_classdev *mcan_class;
+       struct m_can_pci_priv *priv;
+       void __iomem *base;
+@@ -114,6 +150,8 @@ static int m_can_pci_probe(struct pci_de
+       if (!mcan_class)
+               return -ENOMEM;
+ 
++      cfg = (const struct m_can_pci_config *)id->driver_data;
++
+       priv = cdev_to_priv(mcan_class);
+ 
+       priv->base = base;
+@@ -125,7 +163,9 @@ static int m_can_pci_probe(struct pci_de
+       mcan_class->dev = &pci->dev;
+       mcan_class->net->irq = pci_irq_vector(pci, 0);
+       mcan_class->pm_clock_support = 1;
+-      mcan_class->can.clock.freq = id->driver_data;
++      mcan_class->bit_timing = cfg->bit_timing;
++      mcan_class->data_timing = cfg->data_timing;
++      mcan_class->can.clock.freq = cfg->clock_freq;
+       mcan_class->ops = &m_can_pci_ops;
+ 
+       pci_set_drvdata(pci, mcan_class);
+@@ -178,8 +218,8 @@ static SIMPLE_DEV_PM_OPS(m_can_pci_pm_op
+                        m_can_pci_suspend, m_can_pci_resume);
+ 
+ static const struct pci_device_id m_can_pci_id_table[] = {
+-      { PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
+-      { PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
++      { PCI_VDEVICE(INTEL, 0x4bc1), (kernel_ulong_t)&m_can_pci_ehl, },
++      { PCI_VDEVICE(INTEL, 0x4bc2), (kernel_ulong_t)&m_can_pci_ehl, },
+       {  }    /* Terminating Entry */
+ };
+ MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);

diff --git a/queue-5.15/revert-can-m_can-remove-support-for-custom-bit-timing.patch b/queue-5.15/revert-can-m_can-remove-support-for-custom-bit-timing.patch
new file mode 100644 (file)
index 0000000..a3dd8bf
--- /dev/null
+++ b/queue-5.15/revert-can-m_can-remove-support-for-custom-bit-timing.patch
@@ -0,0 +1,76 @@
+From ea768b2ffec6cc9c3e17c37ef75d0539b8f89ff5 Mon Sep 17 00:00:00 2001
+From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+Date: Mon, 15 Nov 2021 10:18:50 +0100
+Subject: Revert "can: m_can: remove support for custom bit timing"
+
+From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+
+commit ea768b2ffec6cc9c3e17c37ef75d0539b8f89ff5 upstream.
+
+The timing limits specified by the Elkhart Lake CPU datasheets do not
+match the defaults. Let's reintroduce the support for custom bit timings.
+
+This reverts commit 0ddd83fbebbc5537f9d180d31f659db3564be708.
+
+Link: https://lore.kernel.org/all/00c9e2596b1a548906921a574d4ef7a03c0dace0.1636967198.git.matthias.schiffer@ew.tq-group.com
+Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/can/m_can/m_can.c |   24 ++++++++++++++++++------
+ drivers/net/can/m_can/m_can.h |    3 +++
+ 2 files changed, 21 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/can/m_can/m_can.c
++++ b/drivers/net/can/m_can/m_can.c
+@@ -1494,20 +1494,32 @@ static int m_can_dev_setup(struct m_can_
+       case 30:
+               /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
+               can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
+-              cdev->can.bittiming_const = &m_can_bittiming_const_30X;
+-              cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X;
++              cdev->can.bittiming_const = cdev->bit_timing ?
++                      cdev->bit_timing : &m_can_bittiming_const_30X;
++
++              cdev->can.data_bittiming_const = cdev->data_timing ?
++                      cdev->data_timing :
++                      &m_can_data_bittiming_const_30X;
+               break;
+       case 31:
+               /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
+               can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
+-              cdev->can.bittiming_const = &m_can_bittiming_const_31X;
+-              cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
++              cdev->can.bittiming_const = cdev->bit_timing ?
++                      cdev->bit_timing : &m_can_bittiming_const_31X;
++
++              cdev->can.data_bittiming_const = cdev->data_timing ?
++                      cdev->data_timing :
++                      &m_can_data_bittiming_const_31X;
+               break;
+       case 32:
+       case 33:
+               /* Support both MCAN version v3.2.x and v3.3.0 */
+-              cdev->can.bittiming_const = &m_can_bittiming_const_31X;
+-              cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
++              cdev->can.bittiming_const = cdev->bit_timing ?
++                      cdev->bit_timing : &m_can_bittiming_const_31X;
++
++              cdev->can.data_bittiming_const = cdev->data_timing ?
++                      cdev->data_timing :
++                      &m_can_data_bittiming_const_31X;
+ 
+               cdev->can.ctrlmode_supported |=
+                       (m_can_niso_supported(cdev) ?
+--- a/drivers/net/can/m_can/m_can.h
++++ b/drivers/net/can/m_can/m_can.h
+@@ -85,6 +85,9 @@ struct m_can_classdev {
+       struct sk_buff *tx_skb;
+       struct phy *transceiver;
+ 
++      struct can_bittiming_const *bit_timing;
++      struct can_bittiming_const *data_timing;
++
+       struct m_can_ops *ops;
+ 
+       int version;

diff --git a/queue-5.15/series b/queue-5.15/series
index 464fab67030ac2568aea1c42b03aeab59dc6624f..5ace94490079bc283b1efc6f004fd2dca2f921ee 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -148,4 +148,7 @@ powerpc-module_64-fix-livepatching-for-ro-modules.patch
 drm-amdgpu-correct-register-access-for-rlc_jump_table_restore.patch
 drm-amdgpu-don-t-override-default-eco_bits-setting.patch
 drm-amd-pm-fix-reading-smu-fw-version-from-amdgpu_firmware_info-on-yc.patch
+revert-can-m_can-remove-support-for-custom-bit-timing.patch
+can-m_can-make-custom-bittiming-fields-const.patch
+can-m_can-pci-use-custom-bit-timings-for-elkhart-lake.patch
 btrfs-fix-invalid-delayed-ref-after-subvolume-creation-failure.patch