riscv: vector: Use vlenb from DT for thead

If thead,vlenb is provided in the device tree, prefer that over reading
the vlenb csr.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-5-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor
index 9897442bd44ffea13ad53bcd32b5086b62da6223..b096548fe0ffdd5468d8daf3aa57ba11e7800f34 100644 (file)
--- a/arch/riscv/Kconfig.vendor
+++ b/arch/riscv/Kconfig.vendor
@@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD
          extensions. Without this option enabled, T-Head vendor extensions will
          not be detected at boot and their presence not reported to userspace.
 
+         If you don't know what to do here, say Y.
+
+config RISCV_ISA_XTHEADVECTOR
+       bool "xtheadvector extension support"
+       depends on RISCV_ISA_VENDOR_EXT_THEAD
+       depends on RISCV_ISA_V
+       depends on FPU
+       default y
+       help
+         Say N here if you want to disable all xtheadvector related procedures
+         in the kernel. This will disable vector for any T-Head board that
+         contains xtheadvector rather than the standard vector.
+
          If you don't know what to do here, say Y.
 endmenu
 

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 4bd054c54c21a3485e567727d3677fc41cef48db..569140d6e6399ee850b7bb262eb72ebf0f891ce7 100644 (file)
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -34,6 +34,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 /* Per-cpu ISA extensions. */
 extern struct riscv_isainfo hart_isa[NR_CPUS];
 
+extern u32 thead_vlenb_of;
+
 void __init riscv_user_isa_enable(void);
 
 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) {  \

diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/include/asm/vendor_extensions/thead.h
index 48421d1553ada6e2796b906bb9852de3831e2186..93fcbf46c87e73d7876dd1a42bec08d7b2098895 100644 (file)
--- a/arch/riscv/include/asm/vendor_extensions/thead.h
+++ b/arch/riscv/include/asm/vendor_extensions/thead.h
@@ -13,4 +13,10 @@
 
 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead;
 
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
+void disable_xtheadvector(void);
+#else
+static inline void disable_xtheadvector(void) { }
+#endif
+
 #endif

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d752291d829bb5deea53dd9595a04670c88ad80c..7d9e8bbfaef289c661ceb023cbd64cf296be74ac 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -39,6 +39,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 /* Per-cpu ISA extensions. */
 struct riscv_isainfo hart_isa[NR_CPUS];
 
+u32 thead_vlenb_of;
+
 /**
  * riscv_isa_extension_base() - Get base extension word
  *
@@ -779,6 +781,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu)
        }
 }
 
+static int has_thead_homogeneous_vlenb(void)
+{
+       int cpu;
+       u32 prev_vlenb = 0;
+       u32 vlenb;
+
+       /* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */
+       if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR))
+               return 0;
+
+       for_each_possible_cpu(cpu) {
+               struct device_node *cpu_node;
+
+               cpu_node = of_cpu_device_node_get(cpu);
+               if (!cpu_node) {
+                       pr_warn("Unable to find cpu node\n");
+                       return -ENOENT;
+               }
+
+               if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) {
+                       of_node_put(cpu_node);
+
+                       if (prev_vlenb)
+                               return -ENOENT;
+                       continue;
+               }
+
+               if (prev_vlenb && vlenb != prev_vlenb) {
+                       of_node_put(cpu_node);
+                       return -ENOENT;
+               }
+
+               prev_vlenb = vlenb;
+               of_node_put(cpu_node);
+       }
+
+       thead_vlenb_of = vlenb;
+       return 0;
+}
+
 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
 {
        unsigned int cpu;
@@ -832,6 +874,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
                riscv_fill_vendor_ext_list(cpu);
        }
 
+       if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) &&
+           has_thead_homogeneous_vlenb() < 0) {
+               pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n");
+               disable_xtheadvector();
+       }
+
        if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
                return -ENOENT;
 

diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 39f0577f580def77605b000a37e7b10a785d553d..6ed16a5f3e87f32d1da37b4c0a4c8f1e19377e1c 100644 (file)
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
 {
        unsigned long this_vsize;
 
-       /* There are 32 vector registers with vlenb length. */
+       /*
+        * There are 32 vector registers with vlenb length.
+        *
+        * If the thead,vlenb property was provided by the firmware, use that
+        * instead of probing the CSRs.
+        */
+       if (thead_vlenb_of) {
+               riscv_v_vsize = thead_vlenb_of * 32;
+               return 0;
+       }
+
        riscv_v_enable();
        this_vsize = csr_read(CSR_VLENB) * 32;
        riscv_v_disable();

diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kernel/vendor_extensions/thead.c
index 0f27baf8d24589a23b043a1698abf6d364ebb654..519dbf70710afc7925ef267eaf4aedcdc54af9d2 100644 (file)
--- a/arch/riscv/kernel/vendor_extensions/thead.c
+++ b/arch/riscv/kernel/vendor_extensions/thead.c
@@ -5,6 +5,7 @@
 #include <asm/vendor_extensions/thead.h>
 
 #include <linux/array_size.h>
+#include <linux/cpumask.h>
 #include <linux/types.h>
 
 /* All T-Head vendor extensions supported in Linux */
@@ -16,3 +17,13 @@ struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead = {
        .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_thead),
        .ext_data = riscv_isa_vendor_ext_thead,
 };
+
+void disable_xtheadvector(void)
+{
+       int cpu;
+
+       for_each_possible_cpu(cpu)
+               clear_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu].isa);
+
+       clear_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap.isa);
+}