drm/msm/a6xx: Split out gpucc register block

Some GPUs have different memory map for GPUCC block. So split out the
gpucc range from a6xx_gmu_cx_registers to a separate block to
accommodate those GPUs.

Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/640052/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 0fcae53c0b140b42d9af313695ad6121c9fc5618..81763876e4029713994b47729a2cec7e1dd3fbb9 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -1214,18 +1214,20 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
        struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 
        a6xx_state->gmu_registers = state_kcalloc(a6xx_state,
-               3, sizeof(*a6xx_state->gmu_registers));
+               4, sizeof(*a6xx_state->gmu_registers));
 
        if (!a6xx_state->gmu_registers)
                return;
 
-       a6xx_state->nr_gmu_registers = 3;
+       a6xx_state->nr_gmu_registers = 4;
 
        /* Get the CX GMU registers from AHB */
        _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],
                &a6xx_state->gmu_registers[0], false);
        _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
                &a6xx_state->gmu_registers[1], true);
+       _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
+               &a6xx_state->gmu_registers[2], false);
 
        if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
                return;
@@ -1234,7 +1236,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
        gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
 
        _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],
-               &a6xx_state->gmu_registers[2], false);
+               &a6xx_state->gmu_registers[3], false);
 }
 
 static struct msm_gpu_state_bo *a6xx_snapshot_gmu_bo(

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index dd4c28a8d9233d8079abaf0065317c1d613dba32..31c7462ab6d7b877c55abc04b98c0a80dac87759 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
@@ -363,6 +363,9 @@ static const u32 a6xx_gmu_cx_registers[] = {
        0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
        /* GMU AO */
        0x9300, 0x9316, 0x9400, 0x9400,
+};
+
+static const u32 a6xx_gmu_gpucc_registers[] = {
        /* GPU CC */
        0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
        0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
@@ -386,6 +389,8 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = {
        REGS(a6xx_gmu_gx_registers, 0, 0),
 };
 
+static const struct a6xx_registers a6xx_gpucc_reg = REGS(a6xx_gmu_gpucc_registers, 0, 0);
+
 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
 static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);