bfd_vma symval;
asection *sym_sec;
bool local_got = false;
- bool is_abs_symbol = false;
Elf_Internal_Rela *rel = relocs + i;
struct elf_link_hash_entry *h = NULL;
unsigned long r_type = ELFNN_R_TYPE (rel->r_info);
Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents
+ r_symndx;
- if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
- && r_type != R_LARCH_CALL36)
+ if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
+ && r_type != R_LARCH_CALL36)
+ || sym->st_shndx == SHN_ABS)
continue;
/* Only TLS instruction sequences that are accompanied by
symval = sym->st_value;
}
symtype = ELF_ST_TYPE (sym->st_info);
- is_abs_symbol = sym->st_shndx == SHN_ABS;
}
else
{
- if (h != NULL && h->type == STT_GNU_IFUNC
- && r_type != R_LARCH_CALL36)
+ if (h != NULL
+ && ((h->type == STT_GNU_IFUNC
+ && r_type != R_LARCH_CALL36)
+ || bfd_is_abs_section (h->root.u.def.section)))
continue;
/* The GOT entry of tls symbols must in current execute file or
else
continue;
- is_abs_symbol = bfd_is_abs_section (h->root.u.def.section);
if (h && LARCH_REF_LOCAL (info, h))
local_got = true;
symtype = h->type;
symval += sec_addr (sym_sec);
- if (r_type == R_LARCH_GOT_PC_HI20 && (!local_got || is_abs_symbol))
+ if (r_type == R_LARCH_GOT_PC_HI20 && !local_got)
continue;
if (relax_func (abfd, sec, sym_sec, rel, symval,
return 0;
}
+/* Return 1 if the relocation must be forced, and 0 if the relocation
+ should never be forced. */
+int
+loongarch_force_relocation (struct fix *fixp)
+{
+ /* Ensure we emit a relocation for every reference to the global
+ offset table. */
+ switch (fixp->fx_r_type)
+ {
+ case BFD_RELOC_LARCH_GOT_PC_HI20:
+ case BFD_RELOC_LARCH_GOT_PC_LO12:
+ case BFD_RELOC_LARCH_GOT64_PC_LO20:
+ case BFD_RELOC_LARCH_GOT64_PC_HI12:
+ case BFD_RELOC_LARCH_GOT_HI20:
+ case BFD_RELOC_LARCH_GOT_LO12:
+ case BFD_RELOC_LARCH_GOT64_LO20:
+ case BFD_RELOC_LARCH_GOT64_HI12:
+ return 1;
+ default:
+ break;
+ }
+ return generic_force_reloc (fixp);
+}
+
static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf)
{
reloc_howto_type *howto;
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) 0
+#define TC_FORCE_RELOCATION(FIX) loongarch_force_relocation (FIX)
+extern int loongarch_force_relocation (struct fix *);
+
/* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax
or PC at start of subsy or with relax but sub_symbol_segment not in
SEC_CODE, we generate 32/64_PCREL. */
--- /dev/null
+#as:
+#readelf: -rWs
+#name: loongarch64 local PIC
+
+Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 12 entries:
+ Offset Info Type Symbol's Value Symbol's Name \+ Addend
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_HI20 [0-9a-f]+ sym \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_LO12 [0-9a-f]+ sym \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_HI20 [0-9a-f]+ foo \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_LO12 [0-9a-f]+ foo \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_PC_LO20 [0-9a-f]+ foo \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_PC_HI12 [0-9a-f]+ foo \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_HI20 [0-9a-f]+ foo \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_LO12 [0-9a-f]+ foo \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_HI20 [0-9a-f]+ sym \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_LO12 [0-9a-f]+ sym \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_LO20 [0-9a-f]+ sym \+ 0
+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_HI12 [0-9a-f]+ sym \+ 0
+#...
+ +[0-9a-f]+: +[0-9a-f]+ 0 NOTYPE LOCAL DEFAULT +[0-9a-f]+ foo
+ +[0-9a-f]+: 0+abba 0 NOTYPE LOCAL DEFAULT ABS sym
+#pass
--- /dev/null
+.text
+foo:
+ .quad 0
+ # 32-bit PC-relative
+ pcalau12i $a0,%got_pc_hi20(sym)
+ ld.d $a0,$a0,%got_pc_lo12(sym)
+ # 64-bit PC-relative
+ pcalau12i $a0,%got_pc_hi20(foo)
+ addi.d $a1,$zero,%got_pc_lo12(foo)
+ lu32i.d $a1,%got64_pc_lo20(foo)
+ lu52i.d $a1,$a1,%got64_pc_hi12(foo)
+ ldx.d $a0,$a0,$a1
+
+ # 32-bit absolute
+ lu12i.w $a0,%got_hi20(foo)
+ ori $a0,$a0,%got_lo12(foo)
+ ld.w $a0,$a0,0
+
+ #64-bit absolute
+ lu12i.w $a0,%got_hi20(sym)
+ ori $a0,$a0,%got_lo12(sym)
+ lu32i.d $a0,%got64_lo20(sym)
+ lu52i.d $a0,$a0,%got64_hi12(sym)
+ ld.d $a0,$a0,0
+
+.set sym,0xabba