]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
Fix right shifts in mcore simulator on 64 bit hosts.
authorJeff Law <jeffreyalaw@gmail.com>
Fri, 1 Dec 2023 14:19:50 +0000 (07:19 -0700)
committerJeff Law <jeffreyalaw@gmail.com>
Fri, 1 Dec 2023 14:19:50 +0000 (07:19 -0700)
If the value to be shifted has the sign bit set, the sign
bit would get copied into bits 32..63 of the temporary.  Those
would then be right shifted into the final value giving an
incorrect final result.

This was observed with upcoming GCC improvements which eliminate
unnecessary extensions.

sim/mcore/interp.c
sim/testsuite/mcore/lsr.s [new file with mode: 0644]
sim/testsuite/mcore/lsri.s [new file with mode: 0644]

index 48d9ff8645a786d221513195840be16e56777821..7561c440729d365ef0ead189601219883e519411 100644 (file)
@@ -757,7 +757,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
          break;
        case 0x0B:                                      /* lsr */
          {
-           unsigned long dst, src;
+           uint32_t dst, src;
            dst = gr[RD];
            src = gr[RS];
            /* We must not rely solely upon the native shift operations, since they
@@ -1060,7 +1060,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
        case 0x3E: case 0x3F:                           /* lsrc, lsri */
          {
            unsigned imm = IMM5;
-           unsigned long tmp = gr[RD];
+           uint32_t tmp = gr[RD];
            if (imm == 0)
              {
                NEW_C (tmp);
diff --git a/sim/testsuite/mcore/lsr.s b/sim/testsuite/mcore/lsr.s
new file mode 100644 (file)
index 0000000..a9a76aa
--- /dev/null
@@ -0,0 +1,28 @@
+# check that lsr works correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+       start
+       # Construct -1
+       bmaski  r2, 32
+
+       # Construct 24
+       movi r3, 24
+
+       # logical shift right by r3 (24)
+       lsr     r2, r3
+
+       # Construct 255
+       bmaski  r1, 8
+
+       # Compare them, they should be equal
+       cmpne   r2,r1
+       jbt     .L1
+       pass
+.L1:
+       fail
+
+
+
+
diff --git a/sim/testsuite/mcore/lsri.s b/sim/testsuite/mcore/lsri.s
new file mode 100644 (file)
index 0000000..bb7bec6
--- /dev/null
@@ -0,0 +1,25 @@
+# check that lsri works correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+       start
+       # Construct -1
+       bmaski  r2, 32
+
+       # logical shift right by 24
+       lsri    r2, 24
+
+       # Construct 255
+       bmaski  r1, 8
+
+       # Compare them, they should be equal
+       cmpne   r2,r1
+       jbt     .L1
+       pass
+.L1:
+       fail
+
+
+
+