platform/x86/amd/pmc: Add STB support for AMD Desktop variants

Previously, AMD's Ryzen Desktop SoCs did not include support for STB.
However, to accommodate this recent change, PMFW has implemented a new
message port pair mechanism for handling messages, arguments, and
responses, specifically designed for distinguishing from Mobile SoCs.
Therefore, it is necessary to update the driver to properly handle this
incoming change.

Add a new function amd_stb_update_args() to simply the arguments that
needs to be passed between S2D supported Mobile SoCs vs Desktop SoCs.

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20241108070822.3912689-10-Shyam-sundar.S-k@amd.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

diff --git a/drivers/platform/x86/amd/pmc/mp1_stb.c b/drivers/platform/x86/amd/pmc/mp1_stb.c
index d19a13a82e1ec7bcd3626228e5afea0365da383d..c005f00988f7d87bcd29066c90abbed6a5784ab9 100644 (file)
--- a/drivers/platform/x86/amd/pmc/mp1_stb.c
+++ b/drivers/platform/x86/amd/pmc/mp1_stb.c
@@ -36,6 +36,11 @@
 #define AMD_S2D_REGISTER_RESPONSE      0xA80
 #define AMD_S2D_REGISTER_ARGUMENT      0xA88
 
+/* STB S2D (Spill to DRAM) message port offset for 44h model */
+#define AMD_GNR_REGISTER_MESSAGE       0x524
+#define AMD_GNR_REGISTER_RESPONSE      0x570
+#define AMD_GNR_REGISTER_ARGUMENT      0xA40
+
 static bool enable_stb;
 module_param(enable_stb, bool, 0644);
 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
@@ -233,12 +238,33 @@ static const struct file_operations amd_stb_debugfs_fops_v2 = {
        .release = amd_stb_debugfs_release_v2,
 };
 
+static void amd_stb_update_args(struct amd_pmc_dev *dev)
+{
+       if (cpu_feature_enabled(X86_FEATURE_ZEN5))
+               switch (boot_cpu_data.x86_model) {
+               case 0x44:
+                       dev->stb_arg.msg = AMD_GNR_REGISTER_MESSAGE;
+                       dev->stb_arg.arg = AMD_GNR_REGISTER_ARGUMENT;
+                       dev->stb_arg.resp = AMD_GNR_REGISTER_RESPONSE;
+                       return;
+               default:
+                       break;
+       }
+
+       dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE;
+       dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT;
+       dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE;
+}
+
 static bool amd_is_stb_supported(struct amd_pmc_dev *dev)
 {
        switch (dev->cpu_id) {
        case AMD_CPU_ID_YC:
        case AMD_CPU_ID_CB:
-               dev->stb_arg.s2d_msg_id = 0xBE;
+               if (boot_cpu_data.x86_model == 0x44)
+                       dev->stb_arg.s2d_msg_id = 0x9B;
+               else
+                       dev->stb_arg.s2d_msg_id = 0xBE;
                break;
        case AMD_CPU_ID_PS:
                dev->stb_arg.s2d_msg_id = 0x85;
@@ -254,10 +280,7 @@ static bool amd_is_stb_supported(struct amd_pmc_dev *dev)
                return false;
        }
 
-       dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE;
-       dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT;
-       dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE;
-
+       amd_stb_update_args(dev);
        return true;
 }