arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displays

The base SoC devicetree now defines a display controller graph:
connect the board specific outputs (eDP internal display, DP
external display) to fully migrate Cherry and make it finally
possible to make Chromebooks and other board types to coexist
without per-board driver modifications.

Tested-by: Chen-Yu Tsai <wenst@chromium.org> # On MT8188 Ciri (int. and ext.)
Link: https://lore.kernel.org/r/20250220110948.45596-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
index faed5c8bc721343d12ccf5c110ec4253d8608647..c5254ae0bb99421c31f0d2630b86e0e2e406e6a5 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
@@ -9,6 +9,7 @@
 
 / {
        aliases {
+               dsi0 = &disp_dsi0;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
@@ -273,14 +274,27 @@
 
                port {
                        dsi_panel_in: endpoint {
-                               remote-endpoint = <&dsi_out>;
+                               remote-endpoint = <&dsi0_out>;
                        };
                };
        };
 
-       port {
-               dsi_out: endpoint {
-                       remote-endpoint = <&dsi_panel_in>;
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       dsi0_in: endpoint {
+                               remote-endpoint = <&dither0_out>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+                       dsi0_out: endpoint {
+                               remote-endpoint = <&dsi_panel_in>;
+                       };
                };
        };
 };
@@ -296,12 +310,74 @@
        pinctrl-0 = <&disp_pwm1_pins>;
 };
 
+&dither0_in {
+       remote-endpoint = <&postmask0_out>;
+};
+
+&dither0_out {
+       remote-endpoint = <&dsi0_in>;
+};
+
+&ethdr0 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+
+                       ethdr0_in: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&vdosys1_ep_ext>;
+                       };
+               };
+
+               port@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+
+                       ethdr0_out: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&merge5_in>;
+                       };
+               };
+       };
+};
+
+&gamma0_out {
+       remote-endpoint = <&postmask0_in>;
+};
+
 &dp_intf1 {
        status = "okay";
 
-       port {
-               dp_intf1_out: endpoint {
-                       remote-endpoint = <&dptx_in>;
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+
+                       dp_intf1_in: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&merge5_out>;
+                       };
+               };
+
+               port@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+
+                       dp_intf1_out: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&dptx_in>;
+                       };
                };
        };
 };
@@ -394,6 +470,35 @@
        status = "okay";
 };
 
+&merge5 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+
+                       merge5_in: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&ethdr0_out>;
+                       };
+               };
+
+               port@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+
+                       merge5_out: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&dp_intf1_in>;
+                       };
+               };
+       };
+};
+
 &mfg0 {
        domain-supply = <&mt6359_vproc2_buck_reg>;
 };
@@ -513,6 +618,10 @@
        };
 };
 
+&ovl0_in {
+       remote-endpoint = <&vdosys0_ep_main>;
+};
+
 &pcie {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_pins>;
@@ -1029,6 +1138,14 @@
        interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&postmask0_in {
+       remote-endpoint = <&gamma0_out>;
+};
+
+&postmask0_out {
+       remote-endpoint = <&dither0_in>;
+};
+
 &sound {
        pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off",
                        "aud_etdm_spk_on", "aud_etdm_spk_off",
@@ -1135,6 +1252,30 @@
        status = "okay";
 };
 
+&vdosys0 {
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdosys0_ep_main: endpoint@0 {
+                       reg = <0>;
+                       remote-endpoint = <&ovl0_in>;
+               };
+       };
+};
+
+&vdosys1 {
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdosys1_ep_ext: endpoint@1 {
+                       reg = <1>;
+                       remote-endpoint = <&ethdr0_in>;
+               };
+       };
+};
+
 &xhci2 {
        /* no power supply since MT7921's power is controlled by PCIe */
        /* MT7921's USB BT has issues with USB2 LPM */