* config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro.

	* config/mips/mips.c (mips_rtx_costs) <DIV>: Check for
	ISA_HAS_FP_RECIP_RSQRT rather than ISA_HAS_FP4.
	* config/mips/mips.md (recip_condition): Remove mode attribute.
	(div<mode>3): Use ISA_HAS_FP_RECIP_RSQRT rather than
	<recip_condition>.
	(*recip<mode>3, *rsqrt<mode>a, *rsqrt<mode>b): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205129 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7a2ea53ef0614cd0cdd3f1a56df18df02ecca1b3..c93f358ffa2664ec9cffddbcf387d4f6b4d8a9d1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-11-20  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro.
+       * config/mips/mips.c (mips_rtx_costs) <DIV>: Check for
+       ISA_HAS_FP_RECIP_RSQRT rather than ISA_HAS_FP4.
+       * config/mips/mips.md (recip_condition): Remove mode attribute.
+       (div<mode>3): Use ISA_HAS_FP_RECIP_RSQRT rather than
+       <recip_condition>.
+       (*recip<mode>3, *rsqrt<mode>a, *rsqrt<mode>b): Likewise.
+
 2013-11-20  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR target/59207

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index d06d57470817a705d3a55b553d2d8415b93aadba..0aeb35aa6d6d484b564bce2b3fffdd67b663ba98 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3972,7 +3972,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
     case DIV:
       /* Check for a reciprocal.  */
       if (float_mode_p
-         && ISA_HAS_FP4
+         && ISA_HAS_FP_RECIP_RSQRT (mode)
          && flag_unsafe_math_optimizations
          && XEXP (x, 0) == CONST1_RTX (mode))
        {

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 11687b8a053e2258eaab2016cd6a205f53b26de9..97df90030008991608380a65a655751d6b61716a 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -921,6 +921,21 @@ struct mips_cpu_info {
    'c = -((a * b) [+-] c)'.  */
 #define ISA_HAS_NMADD3_NMSUB3  TARGET_LOONGSON_2EF
 
+/* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions.  The
+   MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
+   doubles are stored in pairs of FPRs, so for safety's sake, we apply
+   this restriction to the MIPS IV ISA too.  */
+#define ISA_HAS_FP_RECIP_RSQRT(MODE)                                   \
+                               ((((ISA_HAS_FP4 || ISA_MIPS32R2)        \
+                                  && ((MODE) == SFmode                 \
+                                      || ((TARGET_FLOAT64              \
+                                           || ISA_MIPS32R2             \
+                                           || ISA_MIPS64R2)            \
+                                          && (MODE) == DFmode)))       \
+                                 || (TARGET_SB1                        \
+                                     && (MODE) == V2SFmode))           \
+                                && !TARGET_MIPS16)
+
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO                ((ISA_MIPS32                            \
                                  || ISA_MIPS32R2                       \

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 6991f203df442338bbb608a4e4988d51e77fec82..d3ad83cf96bd12d43cfbac54c2ebb1b4b7aed366 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -881,15 +881,6 @@
 (define_mode_attr sqrt_condition
   [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
 
-;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
-;; instructions can be used.  The MIPS32 and MIPS64 ISAs say that RECIP.D
-;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
-;; so for safety's sake, we apply this restriction to all targets.
-(define_mode_attr recip_condition
-  [(SF "ISA_HAS_FP4")
-   (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
-   (V2SF "TARGET_SB1")])
-
 ;; This code iterator allows signed and unsigned widening multiplications
 ;; to use the same template.
 (define_code_iterator any_extend [sign_extend zero_extend])
@@ -2501,7 +2492,8 @@
   "<divide_condition>"
 {
   if (const_1_operand (operands[1], <MODE>mode))
-    if (!(<recip_condition> && flag_unsafe_math_optimizations))
+    if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode)
+         && flag_unsafe_math_optimizations))
       operands[1] = force_reg (<MODE>mode, operands[1]);
 })
 
@@ -2539,7 +2531,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
        (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
                  (match_operand:ANYF 2 "register_operand" "f")))]
-  "<recip_condition> && flag_unsafe_math_optimizations"
+  "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
 {
   if (TARGET_FIX_SB1)
     return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
@@ -2674,7 +2666,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
        (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
                  (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
-  "<recip_condition> && flag_unsafe_math_optimizations"
+  "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
 {
   if (TARGET_FIX_SB1)
     return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
@@ -2692,7 +2684,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
        (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
                             (match_operand:ANYF 2 "register_operand" "f"))))]
-  "<recip_condition> && flag_unsafe_math_optimizations"
+  "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
 {
   if (TARGET_FIX_SB1)
     return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";