RISC-V: Vector pesudoinsns with x0 operand to use imm 0

A couple of Vector pseudoinstructions use x0 scalar which could be
inefficient on wider uarches due to regfile crossing.

Instead use the imm 0 form, which should be functionally equivalent.

 pseudoinsn            orig insn with x0     this patch
 --------------------  --------------------  -------------------
 vneg.v vd,vs          vrsub.vx vd,vs,x0     vrsub.vi vd,vs,0
 vncvt.x.x.w vd,vs,vm  vnsrl.wx vd,vs,x0,vm  vnsrl.wi vd,vs,0,vm
 vwcvt.x.x.v vd,vs,vm  vwadd.vx vd,vs,x0,vm  (imm not supported)

gcc/ChangeLog:
	* config/riscv/vector.md: vncvt substitute vnsrl.
	vnsrl with x0 replace with immediate 0.
	vneg substitute vrsub.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Change
	expected pattern.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/base/simplify-vdiv.c: Ditto.
	* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cf22b39d6cb37886f1699a1c0f5ae5cb19ab040b..8ee43cf0ce1c4fa52d6069bb8e2c3ecc1d4d0871 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3904,7 +3904,10 @@
            (match_operand:V_VLSI 3 "register_operand"       "vr,vr, vr, vr"))
          (match_operand:V_VLSI 2 "vector_merge_operand"     "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.v\t%0,%3%p1"
+  {
+    /* vneg.v = vrsub vd,vs,x0 = vrsub vd,vs,0.  */
+    return (<CODE> == NEG) ? "vrsub.vi\t%0,%3,0%p1" : "v<insn>.v\t%0,%3%p1";
+  }
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -4258,7 +4261,13 @@
             (match_operand 4 "pmode_reg_or_uimm5_operand"             " rK, rK, rK, rK,   rK,   rK")))
          (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vn<insn>.w%o4\t%0,%3,%4%p1"
+  {
+    /* vnsrl vd,vs,x0 = vnsrl vd,vs,0.  */
+    if (REG_P (operands[4]) && REGNO (operands[4]) == 0)
+      return "vn<insn>.wi\t%0,%3,0%p1";
+
+    return "vn<insn>.w%o4\t%0,%3,%4%p1";
+  }
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
@@ -4279,7 +4288,8 @@
            (match_operand:VWEXTI 3 "register_operand"                 "  0,  0,  0,  0,   vr,   vr"))
          (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vncvt.x.x.w\t%0,%3%p1"
+  ;; vncvt.x.x.w = vnsrl vd,vs,x0 = vnsrl vd,vs,0
+  "vnsrl.wi\t%0,%3,0%p1";
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set_attr "vl_op_idx" "4")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
index 5eb6030e348a550b8e70ea2292b4a859d7818437..50f2ac6843bec2b1b98f05d00f5aeeef4b163f06 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -10,8 +10,8 @@
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
index aa6d6d4b7f1670bbfa6f988c4a8b71decd1847a1..dc84325a613358d55da131606a1a88a1150f7886 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -10,8 +10,8 @@
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
index 33cb9918ef91b7e2575b9fdb8e0a3384bacccc0e..980868d84689852e88081107186e4c8cdb0a6ff6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -10,8 +10,8 @@
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
index 082d9e1ed9aa60eed69b61ed0a642a1ad1f4bcdd..ecfeaabb701ebb915b3d9bdec984d9e5e12b8b53 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -10,8 +10,8 @@
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index 4866b221ca4a3e00e4cc149370a8fab113e5d711..e908eba0b116c1b0fc22e455e761215da9c4a4ac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -36,10 +36,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index 651df9f864610c6a1a6d07c6d050d5c458266674..8b8a3f4f16bc045ed2b73318244f0c632e228bba 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
@@ -39,10 +39,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
index cc5f7883a649bb52d5da57ff07dd3019eb7943fb..6c098a9a8287eb60a9d8e195428997c237057cd1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
@@ -36,10 +36,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
index b5f83444c5c979093da3f29cb7a01f74ab042514..6dd9ff6a2d33ffb2326423b76c804573c774a43a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
@@ -36,10 +36,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
index 76089549fbaf508317d579ea62555ac136d74744..613a29950a6830f1327f028f8bb30ed0e15ac486 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
@@ -31,10 +31,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
index 6dfb57e52c00f7015476d08812945c6141cc8951..8008f5b4c6deed66fccfb85abbd9f245376d282f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
@@ -34,10 +34,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
index ca24a332055645918c3e81fe7bc764f647066393..e5456b7f6a3539d1d119c08bde77a71b5c03c63e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
@@ -31,10 +31,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
index 7be4b373a2c5091f68c34c145ed6ef9b3e3923f5..c88f8767575746cafbc06c8af07716266ed0e3e3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
@@ -31,10 +31,10 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
index cc3d6245e12217bf34530ec9a6fc834a511bacd2..011248c243832e5d4e274ede530f7cf3500e33f3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
@@ -3,4 +3,4 @@
 
 #include "vncvt-template.h"
 
-/* { dg-final { scan-assembler-times {\tvncvt.x.x.w} 10 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl.wi} 10 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
index 0b43787c13c1092524b9679da7b4062469bfb994..9e58f5d5211c1254898a24498c85aab857f12bc9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
@@ -3,4 +3,4 @@
 
 #include "vncvt-template.h"
 
-/* { dg-final { scan-assembler-times {\tvncvt.x.x.w} 10 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl.wi} 10 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
index 2d00b9bbb82e67fe9697f1be83e61995bfb06daa..2261872e3de23f41f7c6de8c3f7981aeac1fc5ae 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
@@ -7,4 +7,4 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
 
 /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
index 287adf0480cdc7bf99e4c76301af2c9b8fc35056..4250567686a64cadd2c5f2f469b5488ec08d30a0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
@@ -7,4 +7,4 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
 
 /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
index 946480ce8565d341b8c1a77679295efda1eacfa9..656aad70165c294297f6697c4092bf40be3131bd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
@@ -7,4 +7,4 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
 
 /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
index 3f62d0eafe7a89c22002805dce3fb26a4cccb3be..379df7fb3e6dd50c99bef096d2481579cf8c3d4e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
@@ -4,6 +4,6 @@
 #include "abs-template.h"
 
 /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
index 64302191cdac771f0fe994fceb06573196b56687..e75ae2e15a156ae8d5b635097ac2eef5be77cee9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
@@ -4,6 +4,6 @@
 #include "abs-template.h"
 
 /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
index 66b512eee2063a4dc6063fad0a9d0a1cb88fa8ac..3ea1dc3ab523c83b80d746b7de888eb27fc6ad1e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vneg-template.h"
 
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
index d32c6a187c13215b22feca404a2f7c5629f83456..ed84820b17ffa01ce48aa5c8e0648ff3fd3f262a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vneg-template.h"
 
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
index 510939a0c1546049c2c888d8ec3dcf7ad921517d..e0272ddd3764ada668211cbaacf20159d74f7d3e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
@@ -45,7 +45,7 @@ DEF_OP_V (neg, 128, int64_t, __builtin_abs)
 DEF_OP_V (neg, 256, int64_t, __builtin_abs)
 DEF_OP_V (neg, 512, int64_t, __builtin_abs)
 
-/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi} 38 } } */
 /* { dg-final { scan-assembler-times {vmax\.vv} 38 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
index 2a9a9ada0eb7fd99f7c92e8c4589138d9931fef3..07740f8d6101af2e6bc58d197d67b13f3f7d2ce8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
@@ -37,7 +37,7 @@ DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 128)
 DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 256)
 DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
index 4444ad8dfb488d91ea63f4453495ab3ba0bdfb9f..cc5a7cda04cdc24673cfb32203ee29b30489d6ea 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
@@ -19,7 +19,7 @@ DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 128)
 DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 256)
 DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 14 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
index 1da9312fa69416466a3660987552007277f7d6d2..f356887f84bc6f53d7193ea54f19d843a52f84cc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
@@ -45,7 +45,7 @@ DEF_COND_UNOP (cond_neg, 128, v128di, -)
 DEF_COND_UNOP (cond_neg, 256, v256di, -)
 DEF_COND_UNOP (cond_neg, 512, v512di, -)
 
-/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 38 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
index dce94c587e43f0a69c29d9651d0010e2eb82266d..7b3bc5e17c47a5110a8456046a8646c44e1ec2ae 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
@@ -55,7 +55,7 @@ DEF_COND_CONVERT (trunc, v128udi, v128usi, 128)
 DEF_COND_CONVERT (trunc, v256udi, v256usi, 256)
 DEF_COND_CONVERT (trunc, v512udi, v512usi, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 46 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
index 2a0d8bdf6c673a186c75715c45667ae58e467612..fa7ef1918ee5d29e1da9ed72f5e7c5fcbc5c703a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
@@ -37,7 +37,7 @@ DEF_COND_CONVERT (trunc, v128udi, v128uhi, 128)
 DEF_COND_CONVERT (trunc, v256udi, v256uhi, 256)
 DEF_COND_CONVERT (trunc, v512udi, v512uhi, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
index 510c656b7cccfeaefaaf47c3354540e8bbca3ed5..532c50bf800cc466e1beed2b2eb771807d31b01a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
@@ -19,7 +19,7 @@ DEF_COND_CONVERT (trunc, v128udi, v128uqi, 128)
 DEF_COND_CONVERT (trunc, v256udi, v256uqi, 256)
 DEF_COND_CONVERT (trunc, v512udi, v512uqi, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 14 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
index 9f96da75cbd7288231c193a60d7db4cb3c08a05a..c3191fd30ab40d4708ed7378838e78f15d411f35 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
@@ -38,7 +38,7 @@ DEF_CONVERT (fncvt, double, uint16_t, 256)
 DEF_CONVERT (fncvt, double, uint16_t, 512)
 
 /* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 30 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 30 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
index 858c915d44a917dcbfb828844b8d1f62f99d2c3b..730195cd5546916c2a53e4bc9c4aee55aacc8ea9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
@@ -20,7 +20,7 @@ DEF_CONVERT (fncvt, double, uint8_t, 256)
 DEF_CONVERT (fncvt, double, uint8_t, 512)
 
 /* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 14 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 28 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 28 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
index fb58d2e6d7d9ab4204616c9a4b113aaa3c9df853..305a533516777e8e6e17fffa094556b691de303a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
@@ -53,5 +53,5 @@ DEF_OP_V (neg, 128, int64_t, -)
 DEF_OP_V (neg, 256, int64_t, -)
 DEF_OP_V (neg, 512, int64_t, -)
 
-/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,\s*0} 42 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
index c197db32114e27e3ea61dec22cd636ad4b070333..dbb671c14a8d3a8c292e78d209d0298a77986369 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
@@ -55,7 +55,7 @@ DEF_CONVERT (trunc, uint64_t, uint32_t, 64)
 DEF_CONVERT (trunc, uint64_t, uint32_t, 128)
 DEF_CONVERT (trunc, uint64_t, uint32_t, 256)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 46 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 46 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
index 25bb2a246623ce3df1cca926b196ede5139ec212..93374f44b2bb0eec2b25e3cbe832d2d555744611 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
@@ -37,7 +37,7 @@ DEF_CONVERT (trunc, uint64_t, uint16_t, 128)
 DEF_CONVERT (trunc, uint64_t, uint16_t, 256)
 DEF_CONVERT (trunc, uint64_t, uint16_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 60 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 60 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
index 1993c63ae2daa29e2975f3bcf1139c5b5f020b0f..29770367aad699d3cbbd0dc44ba95989cc8a6a81 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
@@ -19,7 +19,7 @@ DEF_CONVERT (trunc, uint64_t, uint8_t, 128)
 DEF_CONVERT (trunc, uint64_t, uint8_t, 256)
 DEF_CONVERT (trunc, uint64_t, uint8_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 42 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 42 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
index b9fcfe704514673952d46430cd6e76671812eb44..3c7b89a42516b5f238c888cb5ad8bc852d0cf739 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
@@ -15,4 +15,4 @@
 VDIV_WITH_LMUL (1, 16)
 VDIV_WITH_LMUL (1, 32)
 
-/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
index 64f4407d0b6e991163ad6913ddaae5757f4929fb..3db832b744bf18a6686d521166e7e7eab852dcca 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
@@ -8,8 +8,8 @@
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
 **     vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
 */
@@ -28,8 +28,8 @@ void f1 (void * in, void *out)
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
-**     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **     vse32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
 */
@@ -51,8 +51,8 @@ void f2 (void * in, void *out)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
-**     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **     vse32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
 */
@@ -72,8 +72,8 @@ void f3 (void * in, void *out)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
 **     vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
 */
@@ -92,8 +92,8 @@ void f4 (void * in, void *out)
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
-**     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **     vse8.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
 */
@@ -115,8 +115,8 @@ void f5 (void * in, void *out)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**     vneg\.v\tv[0-9]+,\s*v[0-9]+
-**     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **     vse8.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
 */