clk: renesas: r9a09g047: Add support for xspi mux and divider

The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and
pllcm33_xspi divider to select different clock rates. Add support for
both.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 88a5a1c24adee2620e36c17f3fada2f7e28f3130..be387548664a814642948962ba3d596217ab4a33 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -16,7 +16,7 @@
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
+       LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
 
        /* External Input Clocks */
        CLK_AUDIO_EXTAL,
@@ -31,7 +31,13 @@ enum clk_ids {
        CLK_PLLVDO,
 
        /* Internal Core Clocks */
+       CLK_PLLCM33_DIV3,
+       CLK_PLLCM33_DIV4,
+       CLK_PLLCM33_DIV5,
        CLK_PLLCM33_DIV16,
+       CLK_SMUX2_XSPI_CLK0,
+       CLK_SMUX2_XSPI_CLK1,
+       CLK_PLLCM33_XSPI,
        CLK_PLLCLN_DIV2,
        CLK_PLLCLN_DIV8,
        CLK_PLLCLN_DIV16,
@@ -61,6 +67,14 @@ static const struct clk_div_table dtable_2_4[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_2_16[] = {
+       {0, 2},
+       {1, 4},
+       {2, 8},
+       {3, 16},
+       {0, 0},
+};
+
 static const struct clk_div_table dtable_2_64[] = {
        {0, 2},
        {1, 4},
@@ -70,6 +84,10 @@ static const struct clk_div_table dtable_2_64[] = {
        {0, 0},
 };
 
+/* Mux clock tables */
+static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
+static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
+
 static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -84,8 +102,15 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
 
        /* Internal Core Clocks */
+       DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
+       DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
+       DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
        DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
 
+       DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
+       DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
+       DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
+                 dtable_2_16),
        DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
        DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
        DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 449f8c82e8fbd4993f9f0d6471a140fb4daa60aa..9104b1cd276c902761d9f8851c41277a84e0db4c 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -93,10 +93,12 @@ struct smuxed {
                .width = (_width), \
        })
 
+#define CPG_SSEL1              (0x304)
 #define CPG_CDDIV0             (0x400)
 #define CPG_CDDIV1             (0x404)
 #define CPG_CDDIV3             (0x40C)
 #define CPG_CDDIV4             (0x410)
+#define CPG_CSDIV0             (0x500)
 
 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
 #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
@@ -111,6 +113,11 @@ struct smuxed {
 #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
 #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
 
+#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
+
+#define SSEL1_SELCTL2  SMUX_PACK(CPG_SSEL1, 8, 1)
+#define SSEL1_SELCTL3  SMUX_PACK(CPG_SSEL1, 12, 1)
+
 #define BUS_MSTOP_IDX_MASK     GENMASK(31, 16)
 #define BUS_MSTOP_BITS_MASK    GENMASK(15, 0)
 #define BUS_MSTOP(idx, mask)   (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \