]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
target/mips: Fill in TCGCPUOps.pointer_wrap
authorRichard Henderson <richard.henderson@linaro.org>
Sun, 4 May 2025 16:59:29 +0000 (09:59 -0700)
committerRichard Henderson <richard.henderson@linaro.org>
Wed, 28 May 2025 07:08:48 +0000 (08:08 +0100)
Check 32 vs 64-bit addressing state.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/mips/cpu.c

index 4cbfb9435ae0ba4a857e108f63fed247d535337e..1f6c41fd3401e88637c2c0d8fe3fcf4a38370288 100644 (file)
@@ -560,6 +560,14 @@ static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs)
     };
 }
 
+#ifndef CONFIG_USER_ONLY
+static vaddr mips_pointer_wrap(CPUState *cs, int mmu_idx,
+                               vaddr result, vaddr base)
+{
+    return cpu_env(cs)->hflags & MIPS_HFLAG_AWRAP ? (int32_t)result : result;
+}
+#endif
+
 static const TCGCPUOps mips_tcg_ops = {
     .mttcg_supported = TARGET_LONG_BITS == 32,
     .guest_default_memory_order = 0,
@@ -573,6 +581,7 @@ static const TCGCPUOps mips_tcg_ops = {
 
 #if !defined(CONFIG_USER_ONLY)
     .tlb_fill = mips_cpu_tlb_fill,
+    .pointer_wrap = mips_pointer_wrap,
     .cpu_exec_interrupt = mips_cpu_exec_interrupt,
     .cpu_exec_halt = mips_cpu_has_work,
     .cpu_exec_reset = cpu_reset,