]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: ti: var-som-am62p: Add support for ADS7846 touchscreen
authorStefano Radaelli <stefano.radaelli21@gmail.com>
Fri, 3 Oct 2025 12:50:29 +0000 (14:50 +0200)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 30 Oct 2025 13:43:26 +0000 (19:13 +0530)
The VAR-SOM-AM62P integrates an ADS7846 resistive touchscreen controller.
The controller is physically located on the SOM, and its signals are
routed to the SOM pins, allowing carrier boards to make use of it.

This patch adds the ADS7846 node under the appropriate SPI controller.

Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
Link: https://patch.msgid.link/20251003125031.30539-4-stefano.radaelli21@gmail.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi

index aba72d0b767c1d69a545d4aec448beb3df848531..fc5a3942cde001ce33fa295f68a3850b622cac7d 100644 (file)
        pinctrl-0 = <&pinctrl_spi0>;
        ti,pindir-d0-out-d1-in;
        status = "okay";
+
+       /* Resistive touch controller */
+       ads7846: touchscreen@0 {
+               compatible = "ti,ads7846";
+               reg = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_restouch>;
+               interrupt-parent = <&main_gpio0>;
+               interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
+               spi-max-frequency = <1500000>;
+               pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>;
+               ti,x-min = /bits/ 16 <125>;
+               ti,x-max = /bits/ 16 <4008>;
+               ti,y-min = /bits/ 16 <282>;
+               ti,y-max = /bits/ 16 <3864>;
+               ti,x-plate-ohms = /bits/ 16 <180>;
+               ti,pressure-max = /bits/ 16 <255>;
+               ti,debounce-max = /bits/ 16 <10>;
+               ti,debounce-tol = /bits/ 16 <3>;
+               ti,debounce-rep = /bits/ 16 <1>;
+               ti,settle-delay-usec = /bits/ 16 <150>;
+               ti,keep-vref-on;
+               wakeup-source;
+       };
 };
 
 &main_uart5 {