]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: drop error return from flush_gpu_tlb_pasid
authorChristian König <christian.koenig@amd.com>
Mon, 4 Sep 2023 13:50:35 +0000 (15:50 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 26 Sep 2023 20:55:09 +0000 (16:55 -0400)
That function never fails, drop the error return.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index 8614ed249bb415ab77b08ce72f6cc8148275aad2..13917908b04b6395b3c8f011e94d9b69c85b53a9 100644 (file)
@@ -645,9 +645,10 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid,
 
        if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
            !down_read_trylock(&adev->reset_domain->sem)) {
-               return adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
-                                                               flush_type,
-                                                               all_hub, inst);
+               adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
+                                                        flush_type, all_hub,
+                                                        inst);
+               return 0;
        }
 
        /* 2 dwords flush + 8 dwords fence */
index 7732d4ef845eace751d3639916e6462811392985..dd0ede75e5d7639cdff91d847f13e5ca548027fb 100644 (file)
@@ -130,9 +130,9 @@ struct amdgpu_gmc_funcs {
        void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
                                uint32_t vmhub, uint32_t flush_type);
        /* flush the vm tlb via pasid */
-       int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
-                                       uint32_t flush_type, bool all_hub,
-                                       uint32_t inst);
+       void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
+                                   uint32_t flush_type, bool all_hub,
+                                   uint32_t inst);
        /* flush the vm tlb via ring */
        uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
                                       uint64_t pd_addr);
index 5cc77c207dbf3fc135f09866378f9deec273e962..87c1b945e82dd9a8e8603e98a50cecd34da08e98 100644 (file)
@@ -339,9 +339,9 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                         uint16_t pasid, uint32_t flush_type,
+                                         bool all_hub, uint32_t inst)
 {
        uint16_t queried;
        int vmid, i;
@@ -364,7 +364,6 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                                                flush_type);
                }
        }
-       return 0;
 }
 
 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
index 0c34ee62970b258b28583da843c37ce5b567182e..d0e3583a3cac8be731c2cf891c086882e56d0c6a 100644 (file)
@@ -299,9 +299,9 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                         uint16_t pasid, uint32_t flush_type,
+                                         bool all_hub, uint32_t inst)
 {
        uint16_t queried;
        int vmid, i;
@@ -324,7 +324,6 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                                                flush_type);
                }
        }
-       return 0;
 }
 
 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
index 0219a4e00bb7b35e8b3bf8799cbb6586357c0152..8ee6e99d51b7991e0997d2714707e41f68c9c0c6 100644 (file)
@@ -423,15 +423,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                        uint16_t pasid, uint32_t flush_type,
+                                        bool all_hub, uint32_t inst)
 {
        u32 mask = 0x0;
        int vmid;
 
        if (!down_read_trylock(&adev->reset_domain->sem))
-               return 0;
+               return;
 
        for (vmid = 1; vmid < 16; vmid++) {
                u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
@@ -444,7 +444,6 @@ static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
        WREG32(mmVM_INVALIDATE_REQUEST, mask);
        RREG32(mmVM_INVALIDATE_RESPONSE);
        up_read(&adev->reset_domain->sem);
-       return 0;
 }
 
 /*
index eed37d826f0cc2007ca97430074c3c05ca960f35..22130468256c2f203346afc4ff0bbaa162c95f62 100644 (file)
@@ -613,15 +613,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                        uint16_t pasid, uint32_t flush_type,
+                                        bool all_hub, uint32_t inst)
 {
        u32 mask = 0x0;
        int vmid;
 
        if (!down_read_trylock(&adev->reset_domain->sem))
-               return 0;
+               return;
 
        for (vmid = 1; vmid < 16; vmid++) {
                u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
@@ -634,7 +634,6 @@ static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
        WREG32(mmVM_INVALIDATE_REQUEST, mask);
        RREG32(mmVM_INVALIDATE_RESPONSE);
        up_read(&adev->reset_domain->sem);
-       return 0;
 }
 
 /*
index 95a60f6cd35956f0991f7830056502bfbc54c5ba..359374d8ef674b49b10455cd3f525542fbc06765 100644 (file)
@@ -952,9 +952,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                        uint16_t pasid, uint32_t flush_type,
+                                        bool all_hub, uint32_t inst)
 {
        uint16_t queried;
        int i, vmid;
@@ -978,8 +978,6 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                                               flush_type);
                }
        }
-
-       return 0;
 }
 
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,